1. Mini project Viva Schedule – choose date
Test – who were absent?
Assignment Folder – today LAST!!!

2. EKT 221 : Chapter 3 Memory Basics

3. Overview Memory definitions Random Access Memory (RAM)
Static RAM (SRAM) integrated circuits
Cells and slices
Cell arrays and coincident selection
Arrays of SRAM integrated circuits
Dynamic RAM (DRAM) integrated circuits
DRAM Types
Synchronous (SDRAM)
Double-Data Rate (DDR SRAM)
RAMBUS DRAM (RDRAM)
Arrays of DRAM integrated circuits

4. Memory Definitions
Collection of cells capable of storing binary information.
Contains electronic circuits for storing & retrieving information.
Used to provide temporary or permanent storage capability.

5. Memory Basic Process
Info/content from memory is sent to h/w (usually consists of registers & combinational logic) to be processed
The processed info is then returned to the same or different memory address
Input and Output devices may also interact with memory
Printers
Mouse
Keyboard
Monitor
Digital Camera
Scanners
Plotters
Thumb Drive
Exteranal Memory
Memory
Hardware
for
processing
I/O

6. Types of Memories Random Access Memory (RAM) Read Only Memory (ROM)
Write operation – stores new info
Read operation – transfer the stored info out of memory
Read Only Memory (ROM)
Performs the Read operation only

7. Memory data elements Typical data elements are:
bit : a single binary digit
byte : a collection of eight (8) bits accessed together
word : a collection of binary bits whose size is a typical unit of access for the memory. (e.g., 1 byte, 2 bytes, 4 bytes, 8 bytes, etc.)
Memory Data ─ a bit or a collection of bits to be stored into or accessed from memory cells.
Memory Operations ─ operations on memory data supported by the memory unit. Typically, read and write operations over some data element (bit, byte, word, etc.).

8. Calculator Exercise
2 8
2 12
2 16
2 24
2 32

9. Memory Organization
Organized as an indexed array of words. Value of the index for each word is the memory address.
Often organized to fit the needs of a particular computer architecture. Some historically significant computer architectures and their associated memory organization:
Digital Equipment Corporation PDP-8 (DEC Alpha)
used a 12-bit address to address bit words.
IBM 360
used a 24-bit address to address 16,777,216 8-bit (bytes), or
4,194, bit words.
Intel 8080 (8-bit predecessor to the 8086 and the current Intel processors)
used a 16-bit address to address 65,536 8-bit (bytes).

10. Memory Block Diagram A basic memory system is shown here:
k address lines are decoded to address 2k words of memory.
Each word is n bits.
Read and Write are single control lines defining the simplest of memory operations.
(Refer to next slide for example)

11. Memory Organization Example of memory contents above:
address bits = 3; k = 3
data bits = 8; n = 8
Therefore the number of address lines = k = (2m); 23 = 8
Address range = 0 to 2m -1; therefore 0 to 23 – 1, Add. range = 0 to 7
1 word is the size of the memory content; so the memory above has 8 words of 8-bit data

12. Memory Organization Example: address bits = m = 10
data bits =16; n = 16
Address line = (2m)
210 = 1024 or 1K, labeled 0 to 1023
memory content = 16-bit
so the memory has 1K words of 16-bit data or 1K x 16-bit memory
Note :
K (Kilo) = 210
M (Mega) = 220
G (Giga) = 230
Other Example :
64K = 216 = (26 * 210)
2M = = (21 * 220)
4G = = (22 * 230)
What is the address bits (m)?

13. Memory Operations Memory operations require the following:
Data
Address
An operation ─ Typical operations are READ and WRITE. (RAM)
Read Memory ─ an operation that reads a data value stored in memory: (takes from memory)
Place a valid address on the address lines
Activate the Read input.
Note : the content of the selected word are not changed by reading them
Write Memory ─ an operation that writes a data value to memory:
Apply data on the data lines
Activate the Write input
Other than Read/Write (R/W) Chip Select is used to enable a particular RAM. It is sometimes called Memory Enable.

14. Memory Enable

18. RAM Integrated Circuit
Types of random access memory (RAM)
Static – information stored in latches
Dynamic – information stored as electrical charges on capacitors
Charge “leaks” off
Periodic refresh of charge required
Dependence on Power Supply
Volatile – loses stored information when power turned off (example : FPGA – Flex10K)
Non-volatile – retains information when power turned off (example : CPLD – MAX)

19. SRAM ICs

20. Static RAM  Cell Array of storage cells used to implement static RAM
SR Latch
Select input for control
Dual Rail Data Inputs B and B
Dual Rail Data Outputs C and C
Select B C S Q C R Q B
RAM cell

21. Static RAM  Bit Slice
Represents all circuitry that is required for 2n 1-bit words
Multiple RAM cells
Control Lines:
Word select i – one for each word
Bit Select
Data Lines:
Data in
Data out
Word
Select
select B C S Q X C
Word B R Q X
select
RAM cell
RAM cell
Word
select 1
RAM cell
Word
Select
select 2 n
 1 S Q X
Word
select 2 n
 1 X
RAM cell R Q
RAM cell
Read/Write
logic
Data in S Q
Data out
Data in
Read/
Bit
Write
select R Q
(b) Symbol
Write logic
Read logic
Data out
Read/
Bit
Write
select
(a) Logic diagram

22. 2n-Word  1-Bit RAM IC To build a RAM IC from a RAM slice, we need:
Decoder  decodes the n address lines to 2n word select lines
A 3-state buffer 
on the data output permits RAM ICs to be combined into a RAM with c  2n words
4-to-16
Word select
Decoder A A 2 3 3 3 1 2
RAM cell A 2 A 2 2 2 3 4 A 1 A 1 2 1 5 6
RAM cel l A A 2 7
16 x 1 8
RAM 9 10
Data
Data 11
input
output 12 13 14
Read/ 15
Write
Memory
RAM cell
enable
(a) Symbol
Read/Write
logic
Data input
Data in
Data
Data out
output
Read/
Bit
Write
select
Read/Write
Chip select
(b) Block diagram

23. RAM : Cell Arrays and Coincident Selection
Memory arrays can be very large =>
Large decoders
Large fanouts for the bit lines
However, the decoder size and fanouts (outputs) can be reduced by using a coincident selection in a 2-dimensional array:
Uses two decoders, one for words and one for bits
Word select becomes Row select
Bit select becomes Column select

24. Coincident… ??

25. Previous 16 x 1 RAM

26. A3 and A2 used for Row select
Coincident Selection Approach
16 X 1 RAM Chip
16 = 24 = 4 bit add.[A3..A0]
The column decoder is enabled with the CS input
When CS =0, column decoder is disabled and all o/p are 0 and NONE of the cells are selected
A3 and A2 used for Row select
A1 and A0 for Column select
Figure : 9.7
Morris Mano, pg 410

27. Coincident Selection Approach
If Address is 1001:
A3, A2 = 10, row decoder line 2 active
Activating RAM 8,9,10 & 11
A1, A0 = 01, column decoder line 1 active
Activating RAM 1,5,9,13
The intersect RAM is RAM 9 is activated. Other RAM cells not selected are disabled.
Then it depends on the operation functions (Read or Write)
Read : Data out thru OR gate and tri-state buffer
Write : Data available on the Data input line is transferred into the selected RAM cell.
Figure : 9.7
Morris Mano, pg 410

28. Constructing RAM
Previously : Block Diagram of a 16 X 1 RAM using 4 X 4 RAM Cell Array.
How to create 8 X 2 RAM using 4 X 4 RAM Cell Array?
Number of Address bits = 8 = 23 = 3-bits
Number of Data bits = 2-bits

29. 3-bits addressing
2-bits at Row Decoder
1-bit at Column Decoder
Since 2 bits at a time are to be written or read:
2 input lines
Data input 0
Data input 1
2 output lines
Data output 0
Data output 1
Example:
If Address is = 011
Row Decoder = line 1
RAM = 4,5,6 & 7
Column Decoder = line 1
RAM = 2,6,10,14 and
3,7,11,15
Therefore : Cell 6 & 7 are activated
Figure 9.8 : Morris Mano, pg 411

30. Constructing RAM … How about 32K X 8 bit? Address bit = 32 x 210
= 25 x 210= 15-bits
Data bit = 8-bit
Without Coincident selection a single decoder would have 15 inputs and 32,768 outputs. (32 x 1K = 32 x 1024)
And 32,800 no of gates.

31. … Constructing RAM With Coincident selection:
Make row and column equal
Total RAM = 32K x 8 = 256K =
Take Sq Root of = 512
512 = 29 , meaning 9-bits is fed to the ROW Decoder.
Remaining 6-bits is fed to the COLUMN Decoder.
Row Decoder = 9 to 512 line decoder
Column Decoder = 6 to 64 line decoder
No of gates = 608

32. - Making Larger or Wider Memories from Smaller Ones…
Array of SRAM ICs … ?
- Making Larger or Wider Memories from Smaller Ones…

33. ARRAY of SRAM ICs
If an application is larger than the capacity of one chip, then
There is a need to combine a number of chips in an array to form a required size of memory.
Depends on 2 parameters
No of words
No of bits per word
Number of words = address line
1-bit added to address bit would double the no of words
Number of bit = data input & output
1-bit added to the word size, 1 data input & output must be added

34. Bigger.. hOW ? To make larger memories (more address locations)
Number of words  = address line 
1-bit added to address bit would double the no of words.
To make wider memories (bigger memory data size)
Number of bit  = data input & output lines
1-bit added to the word size, 1 data input & output must be added.

35. Making Larger Memories
Using the CS lines, we can make larger memories from smaller ones by tying all address, data, and R/W lines in parallel, and using the decoded higher order address bits to control CS.
Using the 4-Word by 1-Bit memory from before, we construct a 16-Word by 1-Bit memory.  

36. Lets say u have this memory Chip.
How to construct a 256K X 8 RAM using this 64K X 8 RAM Chip?
No of words is the same
No of address is not the same (64K  256K)
64K = 26 x 210 = 16-bit address bit
256 = 28 x 210 = 18-bit address bit
An additional 2 bit is needed for the address bit

37. Constructing 256K X 8 RAM using 64K x 8 RAM Chip
2 additional address bit is applied to a 2 x 4 decoder and represent the MSB of the address bit.
How many 64K x 8 RAM chip to add?
Additional 2 bit = 22 = 4 of 64 x 8 RAM
Use Memory Enable to activate the decoder.

38. Constructing 256K X 8 RAM using 64K x 8 RAM Chip
When bit 17 and 16 = 00
The first 64 x 8 RAM is activated
Address : 0 – 65,535
When bit 17 and 16 = 01
The 2nd 64 x 8 RAM is activated
Address : 65,536 – 131,071
When bit 17 and 16 = 10
The 3rd 64 x 8 RAM is activated
Address : 131,071 – 196,607
When bit 17 and 16 = 11
The 4th 64 x 8 RAM is activated
Address : 196,608 – 262,143
Figure 9.10: Morris Mano, pg 413

39. What if we are to expand the word size?
Example : 64K X 16 using 64K X 8 chip
No of chip to be use refers to the word size.
In this case, 16-bit is to be constructed from
8-bit words
Therefore 2 of 64K X 8 Chip is to be used
Connections:
Address line is input to both chips
CS is common to both chips
R/W control input is also common to both chips
INPUT & OUTPUT DATA LINE is SPLIT

40. Making Wider Memories
To construct wider memories from narrow ones, we tie the address and control lines in parallel and keep the data lines separate.
For example, to make a 4-word by 4-bit memory from 4, 4-word by 1-bit memories  
Note: Both 16x1 and 4x4 memories take 4-chips and hold 16 bits of data.

41. Constructing a 64K X 16 using 64K X 8 chip
Din [15..8]
Din [7..0]
Dout [15..8]
Dout [7..0]

42. Exercise
Construct a 1024 k x 16 SRAM memory using 64 k x 8 memory chips.

43. Dynamic RAM (DRAM)

44. Dynamic RAM (DRAM)
Basic Principle: Storage of information on capacitors.
Charge and discharge of capacitor to change stored value
Use of transistor as “switch” to:
Store charge
Charge or discharge
See next slide for circuit, hydraulic analogy, and logical model.

45. DRAM ICs
Provide high storage capacity at low cost, it dominates the high-capacity memory applications, e.g : Primary RAM in computers
DRAM in many ways similar to SRAM except it must be periodically “refreshed”

46. DRAM Cell It consist of Capacitor C and Transistor T. Transistor T
Capacitor store electric charge
Sufficient charge = logic 1
Insufficient charge = logic 0
Transistor T
Act as a switch
Switch open = the charge on capacitor remains fixed (stored)
Switch closed = charge flow in and out, this allows the cell to be READ or WRITE

47. Dynamic RAM (continued)
Select
Stored 1
Stored 0
To Pump T B C
DRAM cell
(a)
(b)
(c)
Write 1
Write 0
Select
(d)
(e) B
Warning: (d), (e), (f), and (g) are animated. Each animation is triggered with a mouse click
and goes through two steps at 1 second intervals. D Q C
Read 1
Read 0 C
DRAM cell
model
(h)
(f)
(g)

48. Dynamic RAM - Bit Slice C is driven by 3-state drivers
Sense amplifier is used to change the small voltage change on C into H or L
In the electronics, B, C, and the sense amplifier output are connected to make destructive read into non-destructive read
Word
Select
select B C D Q C
DRAM cell
Word
model
select
DRAM cell
Word
select 1
Word
Select
DRAM cell
select 2 n 2 1 D Q
Word
select 2 n 2 1 C
DRAM cell
DRAM cell
model
Read/Write
logic
Data in
Sense
amplifier
Data out
Data in
Read/
Bit
Write
select
(b) Symbol
Write logic
Read logic
Data out
Bit
Read/
Write
select
(a) Logic diagram

49. Hydraulic Analogy for DRAM Cell
(b) Small tank full = storing logic 1
(c) Small tank empty = storing logic 0
In this state the valve is closed

50. Hydraulic Analogy for DRAM Cell
(d) To write a logic 1:
Pump will fill up big tank
Valve open
Water flows from big tank to small tank
Once small tank is full, the valve is closed
(e) To write a logic 0:
Pump will empty big tank
Valve open
Water flows from small tank to big tank
Once small tank is emptied (almost emptied), the valve is closed

51. Hydraulic Analogy for DRAM Cell
Note : Once the water level in storage increase or decrease in the READ operation, the level left in storage will not showing the actual value of the storage anymore.
This is called Destructive Read
To store the original value, we must perform a restore operation to the storage (to return the small tank to its original level)

52. Hydraulic Analogy for DRAM Cell
(f) Reading 1 from storage (small tank)
Large tank at known intermediate level
Valve opened
IF Water flow from small tank to large tank
Water increase slightly in large tank
This slight increase depict READ value of logic 1 from storage
(g) Reading 0 from storage (small tank)
Large tank at known intermediate level
Valve opened
IF Water flow from large tank to small tank
Water decrease slightly in large tank
This slight decrease depict READ value of logic 0 from storage

53. Logic Model of DRAM Dynamic RAM cell circuit Logic Model of DRAM
In actual, there is another consideration for dynamic RAM.
The analogous leakage (due to the use of capacitors)
Due to this leaks, a full storage tank will eventually drain to a point which an increase in the level of the large tank on a READ operation cannot be observed.
To compensate, a refresh is needed.

54. DRAM : Block Diagram

55. DRAM : Block Diagram The addressing is applied serially in two parts:
Row address
Column address
In order to hold the row address throughout the READ or WRITE operation, it is stored in a register.
Signal that control the loading of the registers are:
RAS : Row Address Strobe
CASS : Column Address Strobe
R/W : Read / Write
OE : Output Enable
Note : the LOW signals activate Read, Write and Output enable. This is because when Write operation is activated, there should not be any Data output.

56. DRAM : Block Diagram
The refresh counter and refresh controller is used to control the refresh rate for the DRAM.
Typical refresh rate is between 16 to 64 milliseconds
2 types of refresh:
Distributed refresh (more commonly used)
Burst refresh

57. DRAM Types FPM DRAM (Fast Page Mode DRAM)
EDO DRAM (Extended Data Output DRAM)
SDRAM (Synchronous DRAM)
DDR SDRAM (Double Data Rate SDRAM)
RDRAM (Rambus® DRAM)
ECC (Error Correcting Code)

58. DRAM Types Types to be discussed
Synchronous DRAM (SDRAM)
Double Data Rate SDRAM (DDR SDRAM)
RAMBUS® DRAM (RDRAM)
Justification for effectiveness of these types
DRAM often used as a part of a memory hierarchy (See details in chapter 14)
Reads from DRAM bring data into lower levels of the hierarchy
Transfers from DRAM involve multiple consecutively addressed words
Many words are internally read within the DRAM ICs using a single row address and captured within the memory
This read involves a fairly long delay

59. DRAM Types (continued)
Justification for effectiveness of these types (continued)
These words are then transferred out over the memory data bus using a series of clocked transfers
These transfers have a low delay, so several can be done in a short time
The column address is captured and used by a synchronous counter within the DRAM to provide consecutive column addresses for the transfers
burst read – the resulting multiple word read from consecutive addresses

60. Synchronous DRAM
Transfers to and from the DRAM are synchronize with a clock
Synchronous registers appear on:
Address input
Data input
Data output
Column address counter
for addressing internal data to be transferred on each clock cycle
beginning with the column address counts up to column address + burst size – 1
Example: Memory data path width: 1 word = 4 bytes Burst size: 8 words = 32 bytes Memory clock frequency: 5 ns Latency time (from application of row address until first word available): 4 clock cycles Read cycle time: (4 + 8) x 5 ns = 60 ns Memory Bandwidth: 32/(60 x 10-9) = 533 Mbytes/sec

61. Double Data Rate Synchronous DRAM
Transfers data on both edges of the clock
Provides a transfer rate of 2 data words per clock cycle
Example: Same as for synchronous DRAM
Read cycle time = 60 ns
Memory Bandwidth: (2 x 32)/(60 x 10-9) = Mbytes/sec

62. RAMBUS DRAM (RDRAM)
Uses a packet-based bus for interaction between the RDRAM ICs and the memory bus to the processor
The bus consists of:
A 3-bit row address bus
A 5-bit column address bus
A 16 or 18-bit (for error correction) data bus
The bus is synchronous and transfers on both edges of the clock
Packets are 4-clock cycles long giving 8 transfers per packet representing:
A 12-bit row address packet
A 20-bit column address packet
A 128 or 144-bit data packet
Multiple memory banks are used to permit concurrent memory accesses with different row addresses
The electronic design is sophisticated permitting very fast clock speeds

63. Arrays of DRAM Integrated Circuits
Similar to arrays of SRAM ICs, but there are differences typically handled by an IC called a DRAM controller:
Separation of the address into row address and column address and timing their application
Providing RAS and CAS and timing their application
Performing refresh operations at required intervals
Providing status signals to the rest of the system (e.g., indicating whether or not the memory is active or is busy performing refresh)

64. Do your own reading on types of DRAM
Table 9.2 : Morris Mano, pg 422
Do your own reading on types of DRAM

65. Assigment Folder Questions
9- 4, 5, 9, 10, 12

66. THANK YOU