1. Arria 10 External Memory Interface Simulation Guidelines
Quartus Prime Software v17.0

2. Introduction
Intel’s EMIF IP has an optional simulation example design that can be generated
This design can be used by customers to validate the functionality of the memory interface
This slide deck covers the following topics:
EMIF IP generation
Simulation example design generation
Simulation models, coverage, and assumptions
ModelSim simulation
For more information regarding simulation, refer to the Simulating Memory IP section of the External Memory Interface Handbook
*EMIF = External Memory Interface

3. Software Requirements
Quartus Prime Software v17.0

4. Simulation Example Design
Memory Model
Controller
PHY
Arria 10 EMIF IP Core
Example Design
Example Testbench
Memory
Pass/Fail
Driver (Traffic Generator)
Avalon
AFI
The Simulation Example Design consists of a driver connected to the generated EMIF IP and a memory model
Driver generates random traffic and internally checks the validity of the outgoing data

5. Creating a Quartus Prime Project
The following slides demonstrate how to create a Quartus Prime project
Starting with Quartus Prime v17.0, users must create a Quartus Prime project before generating the EMIF IP and accompanying example design project
Launch Quartus Prime and select New Project Wizard
Or File > New Project Wizard
Press Next, select a directory and name for the project, and select Next
New Project Wizard

6. Creating a Quartus Prime Project
Select Empty project and continue to press Next until you reach the Family, Device, and Board Settings option
Select Arria 10 (GX/SX/GT) under Family and then select your specific Arria 10 device under Available devices
You can filter the available devices list using the options on the right, including the Name filter
Press Finish

7. Generating the EMIF IP
The following slides demonstrate how to generate the EMIF IP and accompanying example design project
Double-click Arria 10 External Memory Interfaces from the IP Catalog
Or Tools > IP Catalog
If the IP Catalog is not visible: View > Utility Windows > IP Catalog

8. Generating the EMIF IP
Double-clicking on Arria 10 External Memory Interfaces opens the IP Parameter Editor
Provide a File Name for the EMIF IP
Click Create

9. Configuring the EMIF IP
Under Memory Protocol, select the appropriate Protocol from the drop-down list
Under the General tab, select the desired Speed Grade and Memory clock frequency
Configure the EMIF IP by selecting appropriate settings under each tab
For more information refer to the Implementing and Parameterizing IP section in the External Memory Interface Handbook

10. Memory Device and Development Kit Presets
Note that there are predefined configurations available for various memory devices
In the Presets window, select the desired memory device present and click Apply
This will populate all the fields with vendor specific settings
A custom memory device preset can also be created by clicking New and entering the configuration data
There also exists presets for existing development kits in the Presets window, where you can select the appropriate one and click Apply

11. Generating the EMIF Simulation Example Design
After configuring the EMIF IP, select the Example Designs tab and make sure the Simulation checkbox is selected under Example Design Files
Select Generate Example Design
Or Generate > Generate Example Design

12. Generating the EMIF Simulation Example Design
After selecting Generate Example Design, a pop-up window will appear asking you to provide a Path to store the example design
Point to the desired location and select OK
In this example, a new emif_0_example_design folder will be created in the existing emif_example directory (created in step 2, slide 5)
This folder will contain all of the EMIF example design files

13. Generating the EMIF Simulation Example Design
Upon successful example design generation, a dialog box will open with design completion detail; press Close
Pin assignments are automatically generated when a development kit preset is selected
If no development kit preset was selected, pin assignments need to be manually assigned

14. Saving the Configured EMIF IP
After closing the window upon successful simulation example design generation, click Finish in the IP Parameter Editor window
A window will pop-up prompting you that recent changes have not been generated
Select Yes if you want to save the IP for future reference/use, otherwise select No
If you selected Yes, select Generate on the next window and then Finish once the generation has completed

15. EMIF Simulation Example Design Files
Synopsys VCS/VCS-MX
Mentor Graphics Modelsim
Cadence NC Sim
Aldec Riviera-Pro
After generating an EMIF simulation example design, an example design directory will be created
From this directory (refer to step 15, slide 12) navigate to sim/ed_sim
Here you will find subdirectories for each supported simulation tool
Each subdirectory contains scripts to use with the corresponding simulation tool

16. EMIF Simulation Requirements
The following slides cover details regarding EMIF simulation
To simulate, you need the following:
Altera Supported Simulator
Intel External Memory Interface IP design
Example Traffic Generator and Checker (Intel or User)
Testbench (Intel or User)
Intel’s Memory Simulator Model (does not support memory vendor models)

17. EMIF Simulation Models
During EMIF IP generation, users can select between two simulation models
Located in Diagnostics tab under Simulation Options
Skip Calibration
Fastest simulation
Loads memory configuration settings and enters user mode
Full Calibration
Performs all stages of memory calibration
Including delay sweeps and centered of all data bits

18. EMIF Simulation Models
Skip Calibration Mode
Full Calibration Mode
System-level simulation focusing on user logic
Memory interface simulation focusing on calibration
Details of calibration are not captured
Captures all stages of calibration
Enables users to store and retrieve data
Includes leveling, per-bit deskew, etc.
Represents accurate efficiency
Board skew is not taken into account

19. EMIF Simulation Coverage
Supported
Not Supported
Functional verification
Timing Verification
Skip calibration (default)
NativeLink
Full calibration
Memory Vendor Models
Post-fit simulation
Qsys Testbench Flow
Multi-rank
Multiple-CS Memory Interface
Memory Frequency < 400MHz
RDIMM & LRDIMM Configuration

20. EMIF Simulation Assumptions
EMIF simulation makes the following assumptions:
Interfaces are unaware of each other
Interface assumes it is the only one interface in the column
Interface assumes it has its own IOAUX and Hard Nios
Interface is placed at the bottom of the column (closest to IOAUX location)
This may contradict fitter placement
No drawbacks between an interface placed at the top of the column vs the bottom of the column
Interfaces have one PLL
This may contradict Post-Fit
It is possible to have interfaces share the same PLL
Simulation assumes PLL reset occurs only during power-up
Simulation issues recalibration per EMIF instead of a PLL reset

21. RTL Simulation VS Post-Fit Implementation
The following slides cover key differences between EMIF simulation and implementation
RTL Simulation
Nios initialization and calibration code execute in parallel
Interfaces might assert cal_done signal simultaneously in simulation
cal_done signal indicates calibration has completed
Do not reply on behavior shown in simulation
Post-Fit Implementation
Nios initialization and calibration code execute sequentially
Order of calibration is determined by fitter operations
Calibration completes when all interfaces in a column assert cal_done
Must sample all cal_done signals in a column to determine calibration has completed

22. RTL Simulation VS Post-Fit Implementation
There may be a discrepancy in latency (Simulated vs Post-Fit)
Do not rely on simulated interface latency
Bank 1
Lane 3
Lane 2
Lane 1
Lane 0
Bank 0
RTL Simulation
Post-Fit Simulation
Fitter Operations
AFI Clock Cycle Penalty
Addr/Cmd
Data

23. AFI Clock Cycle Penalty
For multi-bank interfaces
Fitter detects this penalty and issues a warning
Is an issue when requested write latency is less than latency accrued by bank farthest away from Address/Command Bank
Bank 2
Lane 3
Lane 2
Lane 1
Lane 0
Bank 1
AFI Clock Cycle Penalty
Bank 0
Addr/Cmd
Data

24. Modelsim – Example Simulation Flow
The following slides cover how to run simulation using the ModelSim simulation tool
Launch Modelsim and select set the directory to ed_sim/mentor
File > Change Directory
In the Transcript window, run source msim_setup.tcl
If the Transcript window is not visible: View > Transcript
After msim_setup.tcl finishes executing, run ld_debug
Compiles design files and elaborates with -novopt option

25. Modelsim – Example Simulation Flow
After ld_debug finishes executing, select the signals you wish to simulate
In the Objects window, select the signals and then right-click and select Add Wave
If the Objects window is not visible: View > Objects
After selecting the signals for simulation, execute run –all in the Transcript window
This will run the simulation until it finishes
If the simulation is not visible: View > Wave

26. Modelsim – Example Simulation Flow
Alternatively, you can create your own .do file to run simulation using Modelsim
Example run.do file:
Execute do run.do in the Transcript window to run the simulation
If {[file exsists msim_setup.tcl]} {
source msim_setup.tcl
dev_com
com
# elab_debug avoids optimizations which preserves signals so they can be added to the wave viewer
elab_debug
add wave “ed_sim/*”
run –all
} else {
error “The msim_setup.tcl script does not exist.” }

27. Modelsim – Saving Simulation Data and Results
To store an entire log of the simulation, you can edit the msim_setup.tcl script and modify the vsim line to include –l ed_sim.log: #
# Elaborate top level design
alias elab {
echo "\[exec\] elab“
eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib –L altera_emif_tg_avl_170 -L }
# Elaborate the top level design with novopt option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -novopt -t ps –l ed_sim.log $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib –L
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"