1. DFB
BACK-UP SLIDES

2. DFB Implementation Changes from PDR 1of4
Issue
Implementation
Change
Ensure right-handed coordinate system for E-field data (minimize negative signs to track)
Analog designs changed to define Ez as
V5 – (V1+V2+V3+V4)/4
SIDECAR harmonic distortion performance was not optimized
Minor changes to SIDECAR settings that improve harmonic distortion are identified, will be implemented.
Coordinate FIELDS receivers’ bursts to allow study of multiple time scales for same structure (e.g. shocks, current sheets)
Implemented coordinate burst signal (CBS) to enable synchronized burst capture from DFB/TDS/RFS
Trigger DFB bursts based on data from other FIELDS receivers (e.g. FGM) or other SPP instruments
Enable DBM triggering based on DCB-generated quality flag (optional mode)
Limited telemetry necessitates coordination between DFB bursts and external events (e.g. thruster firing, SCM cal)
Enabled DBM ‘priority event’ commanding by DCB (e.g. DBM disable, SCM cal)

3. DFB Implementation Changes from PDR 2of4
Issue
Implementation
Change
Nominal operation will not accommodate sampling
DC-coupled channels > 293 S/s
Enable DC-coupled channels as selectable inputs for DBM
SCM and E-field sensors mounted in different coordinate systems
Enable pre-rotation of SCM data before spectra / xspec calculation to ensure accurate phase determination (E to SCM)
8x average of SCM data has poor anti-aliasing response for signals < kS/s because SCM analog filter 3dB ~60 kHz
8x average removed. SCM data now cascades from AC digital filter banks to DC digital filter banks. Ensures smoothly falling anti-aliasing response of
< kS/s SCM data.
Extended SCM digital filter cascade results in systematic SCM time delay for < kS/s
Will affect DC Xspec phase.
Implement fixed-value compensating delay of E-field data prior to spec / xspec calculation.
Request to provide s/c potential measurements to DCB (for use by SWEAP)
Implemented Vsc status packet

4. DFB Implementation Changes from PDR 3of4
Issue
Implementation
Change
12-bit s/c fine time insufficient to align samples between FIELDS receivers [DFB to TDS or RFS]
Implemented extended (36-bit FIELDS clock) time stamps for DBM packets. Not needed for waveform, band-pass, spectra, or cross-spec data.
SCM cal signal requirements agreed upon by LPC2E / LASP
SCM calibration signal hardware defined and SCM cal sequence of operations defined. Confirmed calibration waveform needs high-resolution DAC, due to SCM sensitivity to dV/dt effects of low speed, low resolution DACs.
SIDECAR characterization revealed that ASIC ADC channels show relatively higher noise and variation with temperature
Changed DFB routing so that SIDECAR ASIC ADC channels 27 – 31 are no longer used
SIDECAR ADC becomes nonlinear within ~1000 counts of ADC rails
Implement flag in spectral data when input signal approaches (~1000 counts) ADC rails

5. DFB Implementation Changes from PDR 4of4
Issue
Implementation
Change
Mechanical - Change in Random Vibration Levels (EDTRD revB)
Reanalyzed load prior to CCGA qualification test
Mechanical – Vendor change to attached CGAs to ASIC
Changed from Six Sigma copper wrapped 80/20 to BAE 90/10 solder columns
DFB PWB interference with MEP-DFB frame
Modified one threaded insert to avoid connector interference
EMI shield center support location
In-process - Local height accommodation customize

6. DFB – Systems
BACK-UP SLIDES

7. Flight DFB Drawing Count
Summary of drawings
NUMBER
Description
Status
Version
Type
135940 
SPP DFB, TOP LEVEL FLIGHT ASM SSL: SPF-MEP-MEC-017 
Flight Approved A
Assembly
135978
SPP DFB, Flight Model PWBA, SSL PN: SPF-MEP-MEC-02
EM Approved
136042 
SPP, SIDECAR, MECH SPEC  
Drawing
135939 
SPP, DFB, SIDECAR PWB STIFFENER  
Part
136465 
SPP, DFB, PCB INSERT, SHORT  
136471 
SPP DFB, PWB FLIGHT  
136472 
SPP DFB, MECH SPEC, PWB   B
136623 
SPP, DFB, SCHEMATIC, FLIGHT  
Document
134332
SPP DFB, SPECIFICATION DOCUMENT
LASP Approved C
138089 
SPP, DFB, SAFE TO MATE PROCEDURE  
Preliminary
138743 
SPP DFB, PWBA, FLIGHT, FAI  
138790
SPP DFB, PWBA TEST PLAN

8. Documentation Integration & Test
PWBA drawing LASP revA
DFB Assembly drawing LASP DWGrevA
Preliminary Fabrication and Assembly Instruction (FAI) LASP
Used for assembly of vibration test article and EM2, redlines will be incorporated for flight
No special GSE required
Materials Identification List (MIL) reviewed and submitted
Fabrication plans
Use LASP standard procedures and processes
Fabrication, Assembly, Integration and Test plan/procedure at instrument level
handling plan precautions: ESD 50 Volt
Purge requirements: none
Calibration impact on mechanical alignments and I&T: none
Environmental test plans and test flow with test verification matrix
Done at box level, no tests performed at LASP

9. DFB – EE Hardware
BACK-UP SLIDES

10. EM2 performance 95%FS Typical Analog Filter Performance

11. EM2 performance 95% FS Typical End to End Performance
EDC12HG - End to End – FFT of Raw ADC Capture
~80 dB
min = 2581 counts
max = counts

12. DFB - Mechanical
BACK-UP SLIDES

13. Vibration Test Results
CCGA (ceramic column grid array) risk retirement
Manufactured Test PWBA
Columned mechanical ceramic array SIDECAR
Assembled with dummy mass and daughter board
Tested to 4X expected qualification vibration time
Assumed one retest of CCGA, 8 minutes
Test Input adjusted for MEP response
Tested 18 Sept 2014 at Ball Aerospace
Post test inspection
Die penetrant
Ersascope – magnified optical inspection
No visual column damage or deformation
Test report LASP revA
PWBA Input
9.73 GRMS
Post Vibe Test Inspection

14. In Plane Sine Survey DFB

15. In Plane Vibration Response DFB

16. Ceramic Column Grid Array
New package type for LASP
Compliance of solder column less than quad flat pack
Solder column NASA guidelines
Engineers shall select CCGAs with Pb80Sn20 columns wrapped with copper (“Six Sigma”) design
Shall use CCGAs with a (minimum) pin height of 2.21 mm (.087”).
Use polyimide aramid PWB to minimize thermal stress
Good design practice:
minimum board frequency 300Hz
Avoid using corner 6 pins (ea)
Failure Modes
Solder joint fatigue due to PCB out-of-plane deflection (Launch Load)
Solder joint and column fatigue due to PCB in-plane deflection (Launch Load)
Solder joint and column fatigue due to thermal expansion differences in PCB and CGA body, most common failure mode
Bending stress in column
Shear tear-out stress in solder joint
Solder joint and column induced stress due to component screening and component placement

17. SPP DFB Column Grid Array
FPGA RTAX4000 CG1272 (1.45” square)
Maven heritage design (RTAX2000)
Mounted on daughter board 3.25” x 3.4” PWB
First mode 425 – 900 Hz depending on DB connector boundary condition
SIDECAR ASIC (1.4” square)
Mounted on main PWB
solder column
Ø.020”Copper wrapped 80Pb/20Sn from Six Sigma
Not fully populated matrix of columns
Used on HST ACS
Solder properties
Pb80Sn20 unable to locate (fatigue or nonlinear)
Analysis
Closed Form
FEA
Random vibration acceptance level
100g static
Thermal environment benign, very few cycles
SIDECAR
Column pattern

18. PWA Closed Form Analysis
Out-of-Plane Bending, Solder Margins, Steinberg closed form Solution
chip
Freq (Hz) Q
GRMS
3σ GRMS
3σ defl
Z (max ) FS MS
SIDECAR
220
14.8
14.3 43
.0087
.0101
1.12
0.12
300
17.3
18.1
54.2
.0059
1.65
0.65
RTAX4000
425
20.6
23.5
70.4
.0038
.0043
1.11
0.11
900 30
41.2
123.6
.0014
2.84
1.84
SIDECAR
B (6.2”) = length of PCB edge parallel to component (smallest edge)
L (1.40) = Length of electronic component
Assumed 1.86” from one corner column to the other in the diagonal direction
Displacement occurs from corner to corner
h (0.0625”) = thickness of PCB
C (1.75) = BGA constant for different types of electronic components
r (0.9) = Relative position factor of component

19. DFB Finite Element Analysis
Parametric Study
Minimize column stress
Stress caused my PWB deflection under ASIC
Optimize location on PWB
Locally stiffen PWB SIDECAR Clamp
Frame, both sides
Cap, one side
Daughter board connectors significantly impact on results
Model connector plastic
Vary connectivity: free to bonded
Bracket results
Bound effect of daughter board on solder joint
Mode shape change
Changes curvature under SIDECAR
First mode frequency shift
Significant influence on solder stresses
First Mode Shape
DB connecter fully attached DB
outline
DB connecter free

20. DFB – FPGA and ASIC
BACK-UP SLIDES

21. FPGA Design Heritage Block Heritage % Change SIDECAR Interface
New Design
100
WAVEFORMS
MMS/RBSP-EFW 25
DBM
MMS/MAVEN 75
BPF Banks
RBSP-EFW
Spectra
MMS/RBSP/MAVEN 50
SRAM Controller
RBSP/MAVEN 10
Command Proc
MAVEN
Data Proc
Spectra has algorithmic heritage to THEMIS

22. Teledyne SIDECAR ASIC Block Diagram

23. SIDECAR Firmware Development Environment
Teledyne provides an IDE (Integrated Development Environment)
Assembly Language only (no C compiler)
Assembler produces machine code (MCD) files in ASCII format
MCD files are stored in DFB lookup table data
Boot Sequence
At power up the DCB loads DFB lookup table data into DFB SRAM
DFB FPGA reads firmware from SRAM and writes firmware into SIDECAR internal program memory via serial write commands
Assembly code is 95% configuration data for the SIDECAR’s internal configuration registers
Commands from the FPGA allow these configuration registers to be written regardless of microprocessor state
Section of assembly code that is executed is very simple

24. SIDECAR Firmware Development Process
Follow LASP Process “ Software Process Lite”
Source code under version control using SVN
Source code and machine code under configuration management
Fault Detection
SIDECAR internal RAM scrubbed for SEU’s
Status bit in the DFB housekeeping packet will indicate a SIDECAR error
If the SIDECAR status bit goes high, then the DCB will issue a DFB reset and re-configure the DFB