1. The SuperB EMC Front End electronics Prototypes
Valerio Bocci
INFN sezione di Roma
A. Papi, C. Cecchi, P. Lubrano (INFN Perugia)
M. Capodiferro, G. Chiodi, R.Faccini, L. Recchia,D. Ruggieri (INFN Roma)
Valerio Bocci    2009 1

2. SuperB EMC structure BaBar Crystals are radiation damaged.
Need replacement
SuperB EMC Barrel =
BaBar EMC Barrel
5760 CsI(Tl) Crystals
SuperB EMC Forward
= 3600 Lyso Crystals or
360 CsI(TI) BaBar Ring Lyso
Valerio Bocci 2009 2

3. The EMC Front End Electronics
12 x CsI(TI) preamp
Crates (80)
ADB
(80)
ADB
Optical
Link
5760 preamp
/12= 480 ADB
ADB
IOB
ADB
480 ADB
/6 = 80 IOB
ADB
SuperB=Babar
Need new design
ADB
Valerio Bocci 2009 3

4. ECS in the overall system

5. Prototypes boards goal
Test components and architectures
Create a simple system to play whith different parameters
Valerio Bocci 2009

6. Prototypes boards VFE Front End interface Digitizer Board
FPGA data aggregator and PC readout for testing purpose
VFE
VFE
Xilinx
Opal
Kelly
USB 2.0
Digitizer
Board
VFE
VFE
Ctrl Lines
PIN/APD
Valerio Bocci 2009

7. The EMC Forward read out options
CSP +
shaper or
2 x APD (5x5mm) or
2 x PIN (10x10mm) or
Number of Lyso crystals =3600 or
TIA
(Number CsI(TI) Forward endcap babar *4)
1 x PIN ( 20x10mm ) or TA
We start to test Charge sensitive preamp at
Beam Test Facility in Frascati
Valerio Bocci 2009 7

8. APD or PIN readout X 50 .15 V/pC APD Solution X 50 Pin Solution
10x20 mm
Area=apd x 4
M=1
1.4 V/pC
(APD amplification x 10)
Valerio Bocci 2009 8

9. Energy Scan (From Alessandro Rossi EMC presentation)
Valerio Bocci 2009

10. Prototypes boards VFE Front End interface Digitizer Board
FPGA data aggregator and PC readout for testing purpose
VFE
VFE
Xilinx
Opal
Kelly
USB 2.0
Digitizer
Board
VFE
VFE
Ctrl Lines
PIN/APD
Valerio Bocci 2009

11. Very Front End Board PIN/APD Adapter connector VFE 2 PIN PD x2 2 CSP
0-13 GeV -> ( mV ) 2
1.4 V/pC
0.081 mV/Mev
13 Gev 1048 mV
200MeV 16 mv
PIN /APD
PIN PD x2
AD8131
0-200 MeV->( mV ) 2
CSP
(CR110,
OPAMPCSP) x2
x32
OPA657
Differential
Line Driver
(AD8131)
LED
AD8130 / 29
Valerio Bocci 2009

12. Old ADB Energy resolution
Valerio Bocci IX SuperB General Meeting - Perugia   2009 12

13. Energy Resolution new ADB
MeV
% ADC0 LSB/Mev
% ADC1 LSB/
Mev
% ADC selected/ 1
6.87
219.73 10
0.69
21.97
100
0.07
2.20
200
0.03
1.10
300
OVF
0.73
1000
0.22
9000
0.02
Valerio Bocci IX SuperB General Meeting - Perugia   2009 13

14. Prototypes boards VFE Front End interface Digitizer Board
FPGA data aggregator and PC readout for testing purpose
VFE
VFE
Xilinx
Opal
Kelly
USB 2.0
Digitizer
Board
VFE
VFE
Ctrl Lines
PIN/APD
Valerio Bocci 2009

15. Digitizer Board Prototype
DAC X4
Fast Comparator
200 MeV–13 Gev
12Bits
ADC
Fsx6 (DDR) 2
1/4
Differential
Receiver
(8130)
Shaper
(CR )
Programmable
Gain Amplifier
(AD8369)
12bits ADC
(ADS6422) 2
0-200Mev
Differential Receiver(8130)
Range Bit Transmitter
ECS
(ctrl interface)
serializer
Latch
FTCS interf
56 MHz
f/6
9.3 MHz
Valerio Bocci 2009

16. Prototypes boards VFE Front End interface Digitizer Board
FPGA data aggregator and PC readout for testing purpose
VFE
VFE
Xilinx
Opal
Kelly
USB 2.0
Digitizer
Board
VFE
VFE
Ctrl Lines
PIN/APD
Valerio Bocci 2009

17. Serial line receiver and read-out (Opal Kelly Xilinx Board)
Spartan 3 FPGA
Test and understand ADC serial link, data aggregation,Trigger primitives Extraction
PC acquisition using USB interface

18. Time schedule (1)
The goal is to have the first prototype boards in April 2010
End of November finalize schematic
End January 2010 PCB layout
End Febray mounted PCB
Feb-March Test in lab

19. Time schedule (2)
Study the possibility of connecting a few channels to the “kapton cable” of the CMS encapsulated APD’s. If OK, test use them in testbeam.
If not connection to Kapton cable not possible we would like to have the possibility to test a few channels (5) with PIN diodes on Beam.