1. SEP Pre-PDR Peer Review DFE and DAP Electronics May 11, 2010
Kenneth Hatch

2. DFE differences – SEP vs SST
A225 preamp
Built-in shaper
Protection diodes used, but not on schematic
Series output resistor 20 ohm
SEP
A250 preamp
Lower noise
0.25pf FB
1Gohm FB
No shaping
1 volt peak at 6Mev
Protection diodes
Series output resistor changed to 50 ohms for back termination.
(longer coaxes)

3. DAP differences SST 12 channels No shaping network SEP
6 channels ea, 2 brds
Shaping added
This is the major difference
ADC added
For BiasMon, TherMon and
power supplies
Other minor changes
Connectors
No door mon
Part changes

4. CNTRLR
Minor changes
Controls for six channels (plus possible spare if room on board)
Add control for extra ADC
Change BiasMon to avoid dual board conflict
Connect ACTEL to external bus through series R
Use jumper to identify board 1 or board 2 to ACTEL
Schematic details need more work for this

5. Level Control, Bias Supply, Aux_ADC
One quad DAC output controls Bias Supply level
Remaining DAC outputs set Test Pulse level for O, T & F
Test pulse drivers expanded to one per channel
Bias Supply
No change so far
Considering changing diode type to get better efficiency
Aux_ADC
Copy of other ADC circuits

6. ADC ADC hierarchical level Quad Converter level Peak Digitizer level
Splits schematic into 2 sets of 3 channels
Add schematic for spare channel
Generates +/- 2.5Vref
(we use the aux ADC reference for this since it is unique)
Quad Converter level
Should be “Tri-converter”
Provides threshold control for each of the 3 channels
Extra DAC output (we will run it to the spare channel slot)
(Actually 2 DAC’s, so two level controls are run to spare)
Peak Digitizer level
Main schematic for signal processing

7. Peak Digitizer Schematic similar to THEMIS Changes
ADC output changed to 3.3V
Comparators changed to AD8561A
Zero crossing detector change:
DC coupled from clipping amplifier
Should improve high rate time shift
Comparator feed back used to change threshold
Set to positive threshold with no signal (prevents extraneous oscillation)
Changes to baseline level during pulse to accurately detect true zero crossing
Diode and cap added to detect loss of BLR control
(We need to try this out)
Shaping network added

8. Shaping Network Two stages of shaping networks First shaping stage:
Hierarchical box added for first stage
Input from DFE (1.06 volts for 6Mev)
Inverting (net positive signal to ADC)
Pole-zero cancellation (Preamp tail is 250 usec)
One real pole
One complex set of poles
Second shaping stage (on ADC page)
Amplifier enhanced to modified Salen-key design
(Complex pair of poles plus one real pole

9. Appendix 1: Clipped signal
Clipped signal is not equal area
Net shift in average value

10. Appendix 2: Shaping Basic Salen-key circuit: Generates:
two poles that can be complex

11. Appendix 2: Shaping Enhanced Salen-Key Circuit: Generates:
One pair of complex poles
One real pole

12. Appendix 2: Shaping MFB filter: Inverts Generates:
two poles that can be complex

13. Appendix 2: Shaping Add differentiator (e.g. add a zero): Generates:
One pair of complex poles (or two real)
One real pole
One zero at origin (differentiator)

14. Appendix 2: Shaping Add pole-zero cancellation: Generates:
One pair of complex poles (or two real)
One real pole
One zero at origin
One zero that cancels undershoot from preamp tail

15. Pulse shaper waveforms