INPUT-OUTPUT ORGANIZATION

INPUT-OUTPUT ORGANIZATION
Peripheral Devices Input-Output Interface Asynchronous Data Transfer Modes of Transfer Priority Interrupt Direct Memory Access

PERIPHERAL DEVICES Input Devices Output Devices Keyboard
Optical input devices - Card Reader - Paper Tape Reader - Bar code reader - Digitizer - Optical Mark Reader Magnetic Input Devices - Magnetic Stripe Reader Screen Input Devices - Touch Screen - Light Pen - Mouse Analog Input Devices Card Puncher, Paper Tape Puncher CRT Printer (Impact, Ink Jet, Laser, Dot Matrix) Plotter Analog Voice

INPUT/OUTPUT INTERFACE
Input/Output Interfaces INPUT/OUTPUT INTERFACE Provides a method for transferring information between internal storage (such as memory and CPU registers) and external I/O devices Resolves the differences between the computer and peripheral devices Peripherals - Electromechanical Devices CPU or Memory - Electronic Device Data Transfer Rate Peripherals - Usually slower CPU or Memory - Usually faster than peripherals Some kinds of Synchronization mechanism may be needed Unit of Information Peripherals – Byte, Block, … CPU or Memory – Word Data representations may differ

I/O BUS AND INTERFACE MODULES
Input/Output Interfaces I/O BUS AND INTERFACE MODULES I/O bus Data Processor Address Control Interface Interface Interface Interface Keyboard and Magnetic Magnetic Printer display disk tape terminal Each peripheral has an interface module associated with it Interface - Decodes the device address (device code) - Decodes the commands (operation) - Provides signals for the peripheral controller - Synchronizes the data flow and supervises the transfer rate between peripheral and CPU or Memory Typical I/O instruction Op. code Device address Function code (Command)

CONNECTION OF I/O BUS Connection of I/O Bus to CPU CPU I/O bus
Input/Output Interfaces CONNECTION OF I/O BUS Connection of I/O Bus to CPU Computer Op. Device Function Accumulator code address code register I/O control CPU Sense lines Data lines I/O bus Function code lines Device address lines Connection of I/O Bus to One Interface Data lines Peripheral register Device address Buffer register Output peripheral I/O bus device AD = 1101 Interface Logic and controller Function code Command decoder Sense lines Status register

I/O BUS AND MEMORY BUS Functions of Buses
Input/Output Interfaces I/O BUS AND MEMORY BUS Functions of Buses * MEMORY BUS is for information transfers between CPU and the MM * I/O BUS is for information transfers between CPU and I/O devices through their I/O interface * Many computers use a common single bus system for both memory and I/O interface units - Use one common bus but separate control lines for each function - Use one common bus with common control lines for both functions * Some computer systems use two separate buses, one to communicate with memory and the other with I/O interfaces - Communication between CPU and all interface units is via a common I/O Bus - An interface connected to a peripheral device may have a number of data registers , a control register, and a status register - A command is passed to the peripheral by sending to the appropriate interface register - Function code and sense lines are not needed (Transfer of data, control, and status information is always via the common I/O Bus) Physical Organizations I/O Bus

ISOLATED vs MEMORY MAPPED I/O
Input/Output Interfaces ISOLATED vs MEMORY MAPPED I/O Isolated I/O - Separate I/O read/write control lines in addition to memory read/write control lines - Separate (isolated) memory and I/O address spaces - Distinct input and output instructions Memory-mapped I/O - A single set of read/write control lines (no distinction between memory and I/O transfer) - Memory and I/O addresses share the common address space -> reduces memory address range available - No specific input or output instruction -> The same memory reference instructions can be used for I/O transfers - Considerable flexibility in handling I/O operations

I/O INTERFACE I/O CPU Device Programmable Interface
Input/Output Interfaces I/O INTERFACE Port A I/O data register Bidirectional Bus data bus buffers Port B I/O data register I/O Device CPU Chip select CS Internal bus Register select RS1 Control Control Timing register Register select RS0 and Control I/O read RD Status Status I/O write WR register CS RS1 RS Register selected x x None - data bus in high-impedence Port A register Port B register Control register Status register Programmable Interface - Information in each port can be assigned a meaning depending on the mode of operation of the I/O device → Port A = Data; Port B = Command; Port C = Status - CPU initializes(loads) each port by transferring a byte to the Control Register → Allows CPU can define the mode of operation of each port → Programmable Port: By changing the bits in the control register, it is possible to change the interface characteristics

ASYNCHRONOUS DATA TRANSFER
Synchronous and Asynchronous Operations Asynchronous Data Transfer Synchronous - All devices derive the timing information from common clock line Asynchronous - No common clock Asynchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transmitted Two Asynchronous Data Transfer Methods Strobe pulse - A strobe pulse is supplied by one unit to indicate the other unit when the transfer has to occur Handshaking - A control signal is accompanied with each data being transmitted to indicate the presence of data - The receiving unit responds with another control signal to acknowledge receipt of the data

Source-Initiated Strobe Destination-Initiated Strobe
Asynchronous Data Transfer STROBE CONTROL * Employs a single control line to time each transfer * The strobe may be activated by either the source or the destination unit Source-Initiated Strobe for Data Transfer Destination-Initiated Strobe for Data Transfer Block Diagram Block Diagram Data bus Data bus Source Destination Source Destination unit unit unit Strobe Strobe unit Timing Diagram Timing Diagram Valid data Valid data Data Data Strobe Strobe

HANDSHAKING Strobe Methods Source-Initiated
Asynchronous Data Transfer HANDSHAKING Strobe Methods Source-Initiated The source unit that initiates the transfer has no way of knowing whether the destination unit has actually received data Destination-Initiated The destination unit that initiates the transfer no way of knowing whether the source has actually placed the data on the bus To solve this problem, the HANDSHAKE method introduces a second control signal to provide a Reply to the unit that initiates the transfer

SOURCE-INITIATED TRANSFER USING HANDSHAKE
Asynchronous Data Transfer SOURCE-INITIATED TRANSFER USING HANDSHAKE Data bus Block Diagram Source Data valid Destination unit Data accepted unit Valid data Timing Diagram Data bus Data valid Data accepted Sequence of Events Source unit Destination unit Place data on bus. Enable data valid. Accept data from bus. Enable data accepted Disable data valid. Invalidate data on bus. Disable data accepted. Ready to accept data (initial state). * Allows arbitrary delays from one state to the next * Permits each unit to respond at its own data transfer rate * The rate of transfer is determined by the slower unit

DESTINATION-INITIATED TRANSFER USING HANDSHAKE
Asynchronous Data Transfer DESTINATION-INITIATED TRANSFER USING HANDSHAKE Data bus Block Diagram Source Data valid Destination unit Ready for data unit Timing Diagram Ready for data Data valid Valid data Data bus Sequence of Events Source unit Destination unit Ready to accept data. Place data on bus. Enable ready for data. Enable data valid. Accept data from bus. Disable data valid. Disable ready for data. Invalidate data on bus (initial state). * Handshaking provides a high degree of flexibility and reliability because the successful completion of a data transfer relies on active participation by both units * If one unit is faulty, data transfer will not be completed -> Can be detected by means of a timeout mechanism

ASYNCHRONOUS SERIAL TRANSFER
Asynchronous Data Transfer ASYNCHRONOUS SERIAL TRANSFER Asynchronous serial transfer Synchronous serial transfer Asynchronous parallel transfer Synchronous parallel transfer Four Different Types of Transfer Asynchronous Serial Transfer - Employs special bits which are inserted at both ends of the character code - Each character consists of three parts; Start bit; Data bits; Stop bits. 1 1 1 1 Start Stop Character bits bit (1 bit) bits (at least 1 bit) A character can be detected by the receiver from the knowledge of 4 rules; - When data are not being sent, the line is kept in the 1-state (idle state) - The initiation of a character transmission is detected by a Start Bit , which is always a 0 - The character bits always follow the Start Bit - After the last character , a Stop Bit is detected when the line returns to the 1-state for at least 1 bit time The receiver knows in advance the transfer rate of the bits and the number of information bits to expect

UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER - UART -
Asynchronous Data Transfer UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER - UART - A typical asynchronous communication interface available as an IC Transmit Bidirectional Transmitter Shift data data bus Bus register register buffers Control Transmitter Transmitter clock register control and clock Chip select CS Internal Bus Register select RS Timing Status Receiver Receiver CS RS Oper. Register selected x x None WR Transmitter register WR Control register RD Receiver register RD Status register register control clock I/O read and and clock RD Control I/O write Receive WR Receiver Shift data register register Transmitter Register - Accepts a data byte(from CPU) through the data bus - Transferred to a shift register for serial transmission Receiver - Receives serial information into another shift register - Complete data byte is sent to the receiver register Status Register Bits - Used for I/O flags and for recording errors Control Register Bits - Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of stop bits

FIRST-IN-FIRST-OUT(FIFO) BUFFER
Asynchronous Data Transfer FIRST-IN-FIRST-OUT(FIFO) BUFFER * Input data and output data at two different rates * Output data are always in the same order in which the data entered the buffer. * Useful in some applications when data is transferred asynchronously 4 x 4 FIFO Buffer (4 4-bit registers Ri), 4 Control Registers(flip-flops Fi, associated with each Ri) R1 R2 R3 R4 Data 4-bit 4-bit 4-bit 4-bit Data input register register register register output Clock Clock Clock Clock Insert S F 1 S F F 2 S S F F 3 S S F 4 Output ready R F' R F F' 1 2 R R F' F' 3 R R F' 4 Delete Input ready Master clear

MODES OF TRANSFER - PROGRAM-CONTROLLED I/O -
3 different Data Transfer Modes between the central computer(CPU or Memory) and peripherals; Program-Controlled I/O Interrupt-Initiated I/O Direct Memory Access (DMA) Program-Controlled I/O(Input Dev to CPU) Data bus Interface I/O bus Address bus Data register Data valid I/O CPU I/O read device I/O write Status Data accepted F register Read status register Check flag bit Polling or Status Checking = 0 flag Continuous CPU involvement CPU slowed down to I/O speed Simple Least hardware = 1 Read data register Transfer data to memory no Operation complete? yes Continue with program

MODES OF TRANSFER - INTERRUPT INITIATED I/O & DMA
- Polling takes valuable CPU time - Open communication only when some data has to be passed -> Interrupt. - I/O interface, instead of the CPU, monitors the I/O device - When the interface determines that the I/O device is ready for data transfer, it generates an Interrupt Request to the CPU - Upon detecting an interrupt, CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing DMA (Direct Memory Access) - Large blocks of data transferred at a high speed to or from high speed devices, magnetic drums, disks, tapes, etc. - DMA controller Interface that provides I/O transfer of data directly to and from the memory and the I/O device - CPU initializes the DMA controller by sending a memory address and the number of words to be transferred - Actual transfer of data is done directly between the device and memory through DMA controller -> Freeing CPU for other tasks

PRIORITY INTERRUPT Priority
- Determines which interrupt is to be served first when two or more requests are made simultaneously - Also determines which interrupts are permitted to interrupt the computer while another is being serviced - Higher priority interrupts can make requests while servicing a lower priority interrupt Priority Interrupt by Software(Polling) - Priority is established by the order of polling the devices(interrupt sources) - Flexible since it is established by software - Low cost since it needs a very little hardware - Very slow Priority Interrupt by Hardware - Require a priority interrupt manager which accepts all the interrupt requests to determine the highest priority request - Fast since identification of the highest priority interrupt request is identified by the hardware - Fast since each interrupt source has its own interrupt vector to access directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -
Processor data bus VAD 1 VAD 2 VAD 3 * Serial hardware priority function * Interrupt Request Line - Single common line * Interrupt Acknowledge Line - Daisy-Chain Device 1 Device 2 Device 3 PI PO PI PO PI PO To next device Interrupt request INT CPU Interrupt acknowledge INTACK Interrupt Request from any device(>=1) -> CPU responds by INTACK <- 1 -> Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1, and it blocks INTACK to propagate to the next device One stage of the daisy chain priority arrangement S R Q Interrupt request from device PI Priority in RF Delay Vector address VAD PO Priority out Interrupt request to CPU Enable PI RF PO Enable

PARALLEL PRIORITY INTERRUPT
Mask register INTACK from CPU Priority encoder I 1 2 3 y x IST IEN Disk Printer Reader Keyboard Interrupt register Enable Interrupt to CPU VAD Bus Buffer IEN: Set or Clear by instructions ION or IOF IST: Represents an unmasked interrupt has occurred. INTACK enables tristate Bus Buffer to load VAD generated by the Priority Logic Interrupt Register: - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instruction Mask Register: - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

INTERRUPT PRIORITY ENCODER
Priority Interrupt INTERRUPT PRIORITY ENCODER Determines the highest priority interrupt when more than one interrupts take place Priority Encoder Truth table Inputs Outputs I0 I1 I2 I3 x y IST Boolean functions 1 d d d d d d x = I0' I1' y = I0' I1 + I0’ I2’ d d 0 (IST) = I0 + I1 + I2 + I3

INTERRUPT CYCLE At the end of each Instruction cycle
Priority Interrupt INTERRUPT CYCLE At the end of each Instruction cycle - CPU checks IEN and IST - If IEN  IST = 1, CPU -> Interrupt Cycle SP SP - 1 Decrement stack pointer M[SP]  PC Push PC into stack INTACK  1 Enable interrupt acknowledge PC  VAD Transfer vector address to PC IEN  Disable further interrupts Go To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE
Priority Interrupt INTERRUPT SERVICE ROUTINE address Memory I/O service programs 7 JMP DISK DISK Program to service 1 JMP PTR magnetic disk VAD= 3 2 JMP RDR PTR Program to service 3 JMP KBD line printer 8 Main program KBD interrupt 1 RDR Program to service 749 current instr. 750 character reader 4 KBD Stack Program to service 11 keyboard 5 2 255 256 256 Disk interrupt 750 6 9 10 Initial and Final Operations Each interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system Initial Sequence [1] Clear lower level Mask reg. bits [2] IST <- 0 [3] Save contents of CPU registers [4] IEN <- 1 [5] Go to Interrupt Service Routine Final Sequence [1] IEN <- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg. bits [5] Restore return address, IEN <- 1

Direct Memory Access DIRECT MEMORY ACCESS * Block of data transfer from high speed devices, Drum, Disk, Tape * DMA controller - Interface which allows I/O transfer directly between Memory and Device, freeing CPU for other tasks * CPU initializes DMA Controller by sending memory address and the block size(number of words) CPU bus signals for DMA transfer ABUS Address bus High-impedence (disabled) when BG is enabled Bus request BR DBUS Data bus CPU Bus granted BG RD Read WR Write Block diagram of DMA controller Address bus Data bus Data bus Address bus buffers buffers DMA select DS Address register Register select RS Internal Bus Read RD Word count register Control Write WR logic Bus request BR Control register Bus grant BG Interrupt Interrupt DMA request DMA acknowledge to I/O device

DMA I/O OPERATION Starting an I/O - CPU executes instruction to
Direct Memory Access DMA I/O OPERATION Starting an I/O - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command Upon receiving a GO Command DMA performs I/O operation as follows independently from CPU Input [1] Input Device <- R (Read control signal) [2] Buffer(DMA Controller) <- Input Byte; and assembles the byte into a word until word is full [4] M <- memory address, W(Write control signal) [5] Address Reg <- Address Reg +1; WC(Word Counter) <- WC - 1 [6] If WC = 0, then Interrupt to acknowledge done, else go to [1] Output [1] M <- M Address, R M Address R <- M Address R + 1, WC <- WC - 1 [2] Disassemble the word [3] Buffer <- One byte; Output Device <- W, for all disassembled bytes [4] If WC = 0, then Interrupt to acknowledge done, else go to [1]

Direct Memory Access CYCLE STEALING While DMA I/O takes place, CPU is also executing instructions DMA Controller and CPU both access Memory -> Memory Access Conflict Memory Bus Controller - Coordinating the activities of all devices requesting memory access - Priority System Memory accesses by CPU and DMA Controller are interwoven, with the top priority given to DMA Controller -> Cycle Stealing Cycle Steal - CPU is usually much faster than I/O(DMA), thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles, CPU remains idle - For those slow CPU, DMA Controller may steal most of the memory cycles which may cause CPU remain idle long time

DMA TRANSFER Direct Memory Access Interrupt Random-access BG CPU
memory unit (RAM) BR RD WR Addr Data RD WR Addr Data Read control Write control Data bus Address bus Address select RD WR Addr Data DMA ack. DS RS I/O DMA Peripheral BR Controller device BG DMA request Interrupt

INPUT/OUTPUT PROCESSOR - CHANNEL -
- Processor with direct memory access capability that communicates with I/O devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the I/O devices and perform data transfer operations - CPU initiates the channel by executing an channel I/O class instruction and once initiated, channel operates independently of the CPU Central processing unit (CPU) Peripheral devices Memory Memory Bus unit PD PD PD PD Input-output processor I/O bus (IOP)

CHANNEL / CPU COMMUNICATION
Input/Output Processor CHANNEL / CPU COMMUNICATION CPU operations IOP operations Send instruction to test IOP.path Transfer status word to memory If status OK, then send start I/O instruction to IOP. Access memory for IOP program CPU continues with another program Conduct I/O transfers using DMA; Prepare status report. I/O transfer completed; Interrupt CPU Request IOP status Transfer status word Check status word to memory location for correct transfer. Continue

MULTIPROCESSORS Characteristics of Multiprocessors
Interconnection Structures Interprocessor Arbitration Interprocessor Communication and Synchronization Cache Coherence

Characteristics of Multiprocessors
TERMINOLOGY Parallel Computing Simultaneous use of multiple processors, all components of a single architecture, to solve a task. Typically processors identical, single user (even if machine multiuser) Distributed Computing Use of a network of processors, each capable of being viewed as a computer in its own right, to solve a problem. Processors may be heterogeneous, multiuser, usually individual task is assigned to a single processors Concurrent Computing All of the above?

TERMINOLOGY Supercomputing Use of fastest, biggest machines to solve big, computationally intensive problems. Historically machines were vector computers, but parallel/vector or parallel becoming the norm Pipelining Breaking a task into steps performed by different units, and multiple inputs stream through the units, with next input starting in a unit when previous input done with the unit but not necessarily done with the task Vector Computing Use of vector processors, where operation such as multiply broken into several steps, and is applied to a stream of operands (“vectors”). Most common special case of pipelining Systolic Similar to pipelining, but units are not necessarily arranged linearly, steps are typically small and more numerous, performed in lockstep fashion. Often used in special-purpose hardware such as image or signal processors

SPEEDUP AND EFFICIENCY
Characteristics of Multiprocessors SPEEDUP AND EFFICIENCY A: Given problem T*(n): Time of best sequential algorithm to solve an instance of A of size n on 1 processor Tp(n): Time needed by a given parallel algorithm and given parallel architecture to solve an instance of A of size n, using p processors Note: T*(n)  T1(n) Speedup: T*(n) / Tp(n) Efficiency: T*(n) / [pTp(n)] Speedup should be between 0 and p, and Efficiency should be between 0 and 1 Speedup is linear if there is a constant c > 0 so that speedup is always at least cp. Speedup Perfect Speedup Processors

FLYNN’s HARDWARE TAXONOMY
Characteristics of Multiprocessors FLYNN’s HARDWARE TAXONOMY I: Instruction Stream D: Data Stream M S S [ ] I [ ] D SI: Single Instruction Stream - All processors are executing the same instruction in the same cycle - Instruction may be conditional - For Multiple processors, the control processor issues an instruction MI: Multiple Instruction Stream - Different processors may be simultaneously executing different instructions SD: Single Data Stream - All of the processors are operating on the same data items at any given time MD: Multiple Data Stream operating on different data items SISD : standard serial computer MISD : very rare MIMD and SIMD : Parallel processing computers

COUPLING OF PROCESSORS
Characteristics of Multiprocessors COUPLING OF PROCESSORS Tightly Coupled System - Tasks and/or processors communicate in a highly synchronized fashion - Communicates through a common shared memory - Shared memory system Loosely Coupled System - Tasks or processors do not communicate in a synchronized fashion - Communicates by message passing packets - Overhead for data exchange is high - Distributed memory system

MEMORY Shared (Global) Memory - A Global Memory Space accessible by all processors - Processors may also have some local memory Distributed (Local, Message-Passing) Memory - All memory units are associated with processors - To retrieve information from another processor's memory a message must be sent there Uniform Memory - All processors take the same time to reach all memory locations Nonuniform (NUMA) Memory - Memory access is not uniform Network Processors Memory SHARED MEMORY Network Processors/Memory DISTRIBUTED MEMORY

SHARED MEMORY MULTIPROCESSORS
Characteristics of Multiprocessors SHARED MEMORY MULTIPROCESSORS M M M . . . Buses, Multistage IN, Crossbar Switch Interconnection Network P P . . . P Characteristics All processors have equally direct access to one large memory address space Example systems - Bus and cache-based systems: Sequent Balance, Encore Multimax - Multistage IN-based systems: Ultracomputer, Butterfly, RP3, HEP - Crossbar switch-based systems: C.mmp, Alliant FX/8 Limitations Memory access latency; Hot spot problem

MESSAGE-PASSING MULTIPROCESSORS
Characteristics of Multiprocessors MESSAGE-PASSING MULTIPROCESSORS Message-Passing Network . . . P M Point-to-point connections Characteristics - Interconnected computers - Each processor has its own memory, and communicate via message-passing Example systems - Tree structure: Teradata, DADO - Mesh-connected: Rediflow, Series 2010, J-Machine - Hypercube: Cosmic Cube, iPSC, NCUBE, FPS T Series, Mark III Limitations - Communication overhead; Hard to programming

INTERCONNECTION STRUCTURES
* Time-Shared Common Bus * Multiport Memory * Crossbar Switch * Multistage Switching Network * Hypercube System Bus All processors (and memory) are connected to a common bus or busses - Memory access is fairly uniform, but not very scalable

Interconnection Structure
BUS - A collection of signal lines that carry module-to-module communication - Data highways connecting several digital system elements Operations of Bus Devices M3 S7 M6 S5 M4 S2 Bus M3 wishes to communicate with S5 [1] M3 sends signals (address) on the bus that causes S5 to respond [2] M3 sends data to S5 or S5 sends data to M3(determined by the command line) Master Device: Device that initiates and controls the communication Slave Device: Responding device Multiple-master buses -> Bus conflict -> need bus arbitration

SYSTEM BUS STRUCTURE FOR MULTIPROCESSORS
Interconnection Structure SYSTEM BUS STRUCTURE FOR MULTIPROCESSORS Local Bus Common Shared Memory System Bus Controller Local Memory CPU IOP SYSTEM BUS System Bus Controller System Bus Controller Local Memory Local Memory CPU IOP CPU Local Bus Local Bus

MULTIPORT MEMORY Multiport Memory Module - Each port serves a CPU
Interconnection Structure MULTIPORT MEMORY Multiport Memory Module - Each port serves a CPU Memory Module Control Logic - Each memory module has control logic - Resolve memory module conflicts Fixed priority among CPUs Advantages - Multiple paths -> high transfer rate Disadvantages - Memory control logic - Large number of cables and connections Memory Modules MM 1 MM 2 MM 3 MM 4 CPU 1 CPU 2 CPU 3 CPU 4

} } } } CROSSBAR SWITCH Block Diagram of Crossbar Switch
Interconnection Structure CROSSBAR SWITCH Memory modules MM1 MM2 MM3 MM4 CPU1 CPU2 CPU3 CPU4 Block Diagram of Crossbar Switch } data,address, and control from CPU 1 data } Multiplexers and arbitration logic data,address, and control from CPU 2 address Memory Module R/W } data,address, and control from CPU 3 memory enable } data,address, and control from CPU 4

MULTISTAGE SWITCHING NETWORK
Interconnection Structure MULTISTAGE SWITCHING NETWORK Interstage Switch A B 1 A connected to 0 A connected to 1 B connected to 0 B connected to 1

MULTISTAGE INTERCONNECTION NETWORK
Interconnection Structure MULTISTAGE INTERCONNECTION NETWORK Binary Tree with 2 x 2 Switches 000 1 001 1 010 P1 1 1 011 P2 100 1 1 101 110 1 111 8x8 Omega Switching Network 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111

HYPERCUBE INTERCONNECTION
Interconnection Structure HYPERCUBE INTERCONNECTION n-dimensional hypercube (binary n-cube) - p = 2n - processors are conceptually on the corners of a n-dimensional hypercube, and each is directly connected to the n neighboring nodes - Degree = n 011 111 010 01 11 110 101 001 1 00 10 100 000 One-cube Two-cube Three-cube

INTERPROCESSOR ARBITRATION
Bus Board level bus Backplane level bus Interface level bus System Bus - A Backplane level bus - Printed Circuit Board - Connects CPU, IOP, and Memory - Each of CPU, IOP, and Memory board can be plugged into a slot in the backplane(system bus) - Bus signals are grouped into 3 groups Data, Address, and Control(plus power) - Only one of CPU, IOP, and Memory can be granted to use the bus at a time - Arbitration mechanism is needed to handle multiple requests e.g. IEEE standard 796 bus - 86 lines Data: (multiple of 8) Address: 24 Control: 26 Power:

SYNCHRONOUS & ASYNCHRONOUS DATA TRANSFER
Interprocessor Arbitration SYNCHRONOUS & ASYNCHRONOUS DATA TRANSFER Synchronous Bus Each data item is transferred over a time slice known to both source and destination unit - Common clock source - Or separate clock and synchronization signal is transmitted periodically to synchronize the clocks in the system Asynchronous Bus * Each data item is transferred by Handshake mechanism - Unit that transmits the data transmits a control signal that indicates the presence of data - Unit that receiving the data responds with another control signal to acknowledge the receipt of the data * Strobe pulse - supplied by one of the units to indicate to the other unit when the data transfer has to occur

BUS SIGNALS Bus signal allocation IEEE Standard 796 Multibus Signals
Interprocessor Arbitration BUS SIGNALS - address - data - control - arbitration - interrupt - timing - power, ground Bus signal allocation IEEE Standard 796 Multibus Signals Data and address Data lines (16 lines) DATA0 - DATA15 Address lines (24 lines) ADRS0 - ADRS23 Data transfer Memory read MRDC Memory write MWTC IO read IORC IO write IOWC Transfer acknowledge TACK (XACK) Interrupt control Interrupt request INT0 - INT7 interrupt acknowledge INTA

BUS SIGNALS IEEE Standard 796 Multibus Signals (Cont’d)
Interprocessor Arbitration BUS SIGNALS IEEE Standard 796 Multibus Signals (Cont’d) Miscellaneous control Master clock CCLK System initialization INIT Byte high enable BHEN Memory inhibit (2 lines) INH1 - INH2 Bus lock LOCK Bus arbitration Bus request BREQ Common bus request CBRQ Bus busy BUSY Bus clock BCLK Bus priority in BPRN Bus priority out BPRO Power and ground (20 lines)

INTERPROCESSOR ARBITRATION STATIC ARBITRATION
Serial Arbitration Procedure Highest priority To next arbiter 1 PI Bus PO PI Bus PO PI Bus PO PI Bus PO arbiter 1 arbiter 2 arbiter 3 arbiter 4 Bus busy line Parallel Arbitration Procedure Bus Bus Bus Bus arbiter 1 arbiter 2 arbiter 3 arbiter 4 Ack Req Ack Req Ack Req Ack Req Bus busy line 4 x 2 Priority encoder 2 x 4 Decoder

INTERPROCESSOR ARBITRATION DYNAMIC ARBITRATION
Priorities of the units can be dynamically changeable while the system is in operation Time Slice Fixed length time slice is given sequentially to each processor, round-robin fashion Polling Unit address polling - Bus controller advances the address to identify the requesting unit LRU FIFO Rotating Daisy Chain Conventional Daisy Chain - Highest priority to the nearest unit to the bus controller Rotating Daisy Chain - Highest priority to the unit that is nearest to the unit that has most recently accessed the bus(it becomes the bus controller)

INPUT-OUTPUT ORGANIZATION

Similar presentations

Presentation on theme: "INPUT-OUTPUT ORGANIZATION"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

INPUT-OUTPUT ORGANIZATION

Similar presentations

Presentation on theme: "INPUT-OUTPUT ORGANIZATION"— Presentation transcript:

Similar presentations

About project

Feedback