1. Dept. of Electronics. & Info. Eng. Prof. Jongbok Lee
Ch. 9 Flip Flops & Clocks
Dept. of Electronics. & Info. Eng.
Prof. Jongbok Lee

2. % The Usage of Clocks declaration The expression of Rising Edge
clk : in std_logic;
The expression of Rising Edge
if (clk’event and clk=‘1’) then
if rising_edge(clk) then
The expression of Falling Edge
if (clk’event and clk=‘0’) then
if falling_edge(clk) then

3. % Emulation using a clock
Back ground
In FPGA, the input pin for using a clock is determined.
Clock input pin must be specially treated using component ibuf and component bufg.

4. How-to
Package & library declaration: erase the comment on following two lines.
library unisim;
use unisim.Vcomponents.all;
Declare ibuf & bufg in the architecture declaration part
Component instantiation in the architecture main body
component ibuf port (i:in std_logic; o : out std_logic); end component;
component bufg port (i:in std_logic; o: out std_logic); end component;
u1 : ibuf port map (i=>user_clk, o=>tmp);
u2 : bufg port map (i=>tmp, o=> real_clk);

5. 1. D Flip Flop Function Types
The data applied to D input is transferred to output by the clock signal.
Used for registers, small memories.
Types
simple D flip flop
input : d, clk
output : q
D flip flop with synchronous/asynchronous reset
intput : d,clk,reset

6. [1] A Simple D Flip Flop (for simulation)
enitity dff is
port ( d,clk : in std_logic;
q : out std_logic);
end dff;
architecture behavioral of dff is
begin
process(clk,d)
if (clk’event and clk=‘1’) then
q <= d;
end if;
end process;
end behavioral;

8. [2] A Simple D Flip Flop (for emulation)
library unisim;
use unisim.vcomponents.all;
enitity dff is
port ( d,clk : in std_logic;
q : out std_logic);
end dff;
architecture behavioral of dff is
component ibuf port (i:in std_logic; o:out std_logic); end component;
component bufg port (i:in std_logic; o:out std_logic); end component;
signal tmp,rclk : std_logic;
begin
u1 : ibuf port map (i=>clk,o=>tmp);
u2 : bufg port map (i=>tmp, o=>rclk);
process(rclk,d)
if (rclk’event and rclk=‘1’) then
q <= d;
end if;
end process;
end behavioral;

9. signal pin no. clk M14 d G1 q A12 키트 연결 dff.ucf
NET "clk" LOC = "M14" ;
NET "d" LOC = "G1" ;
NET "q" LOC = "A12" ;
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
signal
pin no.
clk
M14 d G1 q
A12
P16 D9 C9
C12
B13
B14
A14
A12
R16
C15
B16
G14
G15
L13
M14 G1
% 실험
G1을 내리고(d=1) M14를 올렸다 내리면(clk:0->1) A12가 켜짐(q=1)