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On behalf of the ATLAS muon collaboration

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Presentation on theme: "On behalf of the ATLAS muon collaboration"— Presentation transcript:

1 On behalf of the ATLAS muon collaboration
Electronics Design and System Integration of the ATLAS New Small Wheels Panagiotis Gkountoumis National Technical University of Athens – Brookhaven National Laboratory On behalf of the ATLAS muon collaboration IPRD16, /10/2016, SIENA, ITALY

2 Overview Introduction New Small Wheel electronics
On detector placement Prototype boards Vertical Slice integration Summary 05/10/2016 IPRD , SIENA, ITALY

3 Introduction 05/10/2016 IPRD , SIENA, ITALY

4 New Small Wheel and trigger plans
Requirements : Phase-1 ( ) Level KHz Phase-2 ( ) One level-0 1 MHz Dual level: 1MHz & Level-1 @ 400 KHz Dual level : 4MHz & Level-1 @ 600 KHz Small Wheels Consist of: Cathode Strip Chambers (CSC) Thin Gap Chambers (TGC) Monitor Drift Tube (MDT) Not efficient in high rates (maximum 20 KHz/cm2) 90% of the current End-cap muon triggers are fakes New Small Wheels A set of precision tracking and trigger detectors able to work at high rates Will provide online high quality (σθ ~1 mrad) IP pointing segments Significant reduction of fake Level-1 muon triggers 05/10/2016 IPRD , SIENA, ITALY

5 New Small Wheel electronics
05/10/2016 IPRD , SIENA, ITALY

6 Possible duplicate removal
Overall readout and trigger scheme Radiation tolerant ASICs Slow Control Adapter (SCA) Read Out Controller (ROC) Address Real Time (ART) GigaBit Transceiver (GBTX) Trigger Data Serializer (TDS) VMM (amplifier, discriminator, shaper) Front-End LInk eXchange (FELIX) Interface network Timing Trigger & Control (TTC) Art Data Driver Card (ADDC) Read Out Device (ROD) Detector Control System (DCS) Front-ends (FE) Pad trigger and router use commercial FPGAs On-detector Off-detector Up to 8 FEs USA15 From Big Wheel ... sTGC - On NSW rim Trigger processor pad TDS Pad trigger 1/FEB L1DDC Sector logic Only for sTGC Possible duplicate removal strip TDS strip TDS strip TDS Router Trigger processor 3/FEB micromegas ... VMM Event monitor ROD ART TTC GBTX VMM VMM VMM SCA BCR clk FELIX network FELIX Config ART GBTX ROC # of VMMs per FEB: MM: 8 sTGC: strips 6 or 7 sTGC pad 2 or 1 sTGC wire 1 clk ADDC BCR Trigger monitor DCS calibration GBTX SCA Bidirectional fiber miniSAS cables L1DDC One way fiber Front end board 05/10/2016 IPRD , SIENA, ITALY

7 Possible duplicate removal
Micromegas and sTGC readout scheme MMs channels sTGC channels From FELIX Time trigger and control signals Configuration data To FELIX Level-1 Monitoring data 2 different L1DDC (sTGC & Micromegas) Upon a level-0 accept data to ROC Upon a level-1 accept data to FELIX On-detector Off-detector Up to 8 FEs USA15 From Big Wheel ... sTGC - On NSW rim Trigger processor pad TDS Pad trigger 1/FEB L1DDC Sector logic Only for sTGC Possible duplicate removal strip TDS strip TDS strip TDS Router Trigger processor 3/FEB Level-0 micromegas ... VMM Event monitor ROD ART TTC GBTX VMM VMM VMM Level-1 SCA BCR clk FELIX network FELIX Config ART GBTX ROC # of VMMs per FEB: MM: 8 sTGC: strips 6 or 7 sTGC pad 2 or 1 sTGC wire 1 clk ADDC BCR Trigger monitor DCS calibration GBTX SCA Bidirectional fiber miniSAS cables L1DDC One way fiber Front end board 05/10/2016 IPRD , SIENA, ITALY

8 Possible duplicate removal
Micromegas trigger scheme On-detector Off-detector 8 FEs USA15 From Big Wheel ... sTGC - On NSW rim Channel address of the first hit from each VMM is send to the ADDC boards 32 inputs (4 FEs) A priority based hit selection is implemented in real time Selected data are sent to trigger Processor Trigger processor pad TDS Pad trigger 1/FEB L1DDC Sector logic Only for sTGC Possible duplicate removal strip TDS strip TDS strip TDS Router Trigger processor 3/FEB micromegas ... VMM Event monitor ROD ART TTC GBTX VMM VMM VMM SCA BCR clk FELIX network FELIX Config ART GBTX ROC 8 VMMs per FEB clk ADDC BCR Trigger monitor DCS calibration GBTX SCA Bidirectional fiber miniSAS cables L1DDC One way fiber Front end board 05/10/2016 IPRD , SIENA, ITALY

9 Possible duplicate removal
sTGC trigger scheme Time & amplitude are sent to the pTDS Strips are buffered and tagged with the BCID Pad trigger logic identifies a track The candidate geometrical coordinates & corresponding BCID are sent to sTDS sTDS transmits the strip charges, BCID, band-ID, and φ-ID Signals are sent to track finding processors where centroids and track segments are calculated Finally, sector logic combines data with candidate tracks from the Big Wheel RIM-L1DDC for configuration of the RIM electronics pad TDS ROC SCA Front end board L1DDC ART GBTX strip TDS ADDC ROD Event monitor Config DCS calibration Trigger monitor Sector logic On-detector sTGC - On NSW rim Trigger processor USA15 1/FEB 3/FEB micromegas Bidirectional fiber One way fiber Only for sTGC network TTC Possible duplicate removal # of VMMs per FEB: sTGC: strips 6 or 7 sTGC pad 2 or 1 sTGC wire 1 Off-detector clk BCR miniSAS cables Pad trigger RIM - L1DDC VMM ... Router FELIX 3 FEs From Big Wheel Find a segment – search for the strip only at this segment 05/10/2016 IPRD , SIENA, ITALY

10 On detector placement 05/10/2016 IPRD , SIENA, ITALY

11 Electronic board placement on MM detectors
Cooling channel L1DDC FEs will be placed radially on both sides of each plane L1DDC and ADDC boards will be placed only on the 1st and 4th plane of each wedge (4 planes) 1 L1DDC & 1 ADDC will serve the 8 FE located on each side of a plane and will be placed on the center to minimize the cable length 512 L1DDC 512 ADDC 4096 MMFE8 Cables FE FE12 65 mm FE16 FE14 FE10 FE8 FE6 FE4 FE2 FE3 FE1 FE5 FE7 FE15 FE13 FE9 FE11 MMs sector (8 planes) 05/10/2016 IPRD , SIENA, ITALY

12 Electronic board placement on sTGC detectors
FEs radially on both sides of each plane Faraday cage will be used for the sTGC FE to isolate the sensitive electronics L1DDC will be placed on the upper part close to the rim for accessibility reasons 1 L1DDC will serve 3 front ends of each plane 768 sFE 768 p&wFE 512 L1DDC p&wFE sFE Cooling pipe Cooling plate L1DDC 05/10/2016 IPRD , SIENA, ITALY

13 Rim electronics 1 RIM box per sector
Commercial boxes and electronics will be used 32 RIM-L1DDC 32 PAD trigger 256 Routers Large sector Structure Rim boxes RIM-L1DDC Pad trigger 8 Routers 05/10/2016 IPRD , SIENA, ITALY

14 Prototype boards 05/10/2016 IPRD , SIENA, ITALY

15 Prototype boards Most of the prototype boards are already fabricated
Using commercial FPGAs until all ASICs are fabricated and tested Mini-FELIX and trigger processor running on evaluation boards RIM-L1DDC will be submitted for fabrication this month MMFE8 pad&wire FE PAD trigger ADDC RIM-L1DDC strip FE Mini-FELIX Trigger Processor VC709 VC707 Router L1DDC 05/10/2016 IPRD , SIENA, ITALY

16 New prototypes L1DDC prototype-2 for MM detectors miniSAS Power VTRX
VTTX miniSAS Power FEAST ASIC VTRX Shield GBTX ASIC bottom side SCA ASIC bottom side L1DDC prototype-2 for MM detectors MMFE8 New prototype using radiation tolerant DC-DC converters is already fabricated and under testing Next prototype with VMM3 will be submitted this month L1DDC Fabrication of 10 boards this month ADDC Schedule for prototype-2 when ART ASIC is tested L1DDC and ADDC new prototypes will use only radiation and magnetic tolerant components based on final requirements (dimensions, rate, components) 60 mm 140 mm VTRX L1DDC prototype-2 for sTGC detectors 05/10/2016 IPRD , SIENA, ITALY

17 Vertical slice integration
05/10/2016 IPRD , SIENA, ITALY

18 Vertical Slice integration week
Allocated a space in building 188 at CERN for the NSW electronics 8-14 of August mainly focused on MM (data + trigger) 15-21 of August mainly focused on sTGC (data) People from Arizona, NTUA/BNL, Harvard, USTC, McGill, Carleton, Irvine, Avans 05/10/2016 IPRD , SIENA, ITALY

19 What was achieved Mini-FELIX MMFE8 readout firmware ✔
MMFE8 communication with the Software (UDP protocol over 1Gbps Ethernet) ✔ MMFE8 communication with the 80 Mbps ✔ Link of L1DDC with FELIX established ✔ MMFE8, ADDC and trigger processor was also established ✔ Twinax cables, communication standards (custom LVDS, SLVS) and grounding schemes were also verified ✔ sFE & p&wFE communication with software over raw Ethernet ✔ sFE & p&wFE communication with L1DDC ✖ MMFE8 and L1DDC communication at 160 & 320 Mbps ✖ Fiber Custom LVDS VC709 SLVS MMFE8 L1DDC 1 Gbps Ethernet Custom LVDS Trigger Processor Fiber Twinax cable ADDC VC707 MMFE8 05/10/2016 IPRD , SIENA, ITALY

20 Summary NSW electronics will be able to cope with the high data rates of the HL-LHC On detector electronics will use only radiation and magnetic tolerant components 3D simulations can confirm that the electronics can fit nicely on the chambers The two “integration weeks” were very useful for starting and achieving the integration of NSW electronics Integration week proved that the goal is achievable A lot of work still need to be done - looking forward to the next integration week 05/10/2016 IPRD , SIENA, ITALY

21 References ASICS Boards Parameter books
GBT project: GBTX: GBT-SCA: FEAST: GBLD: VMM: ROC: Boards L1DDC design review: RIM-L1DDC: Parameter books sTGC: MMs: 05/10/2016 IPRD , SIENA, ITALY

22 Thank you for your attendance!
05/10/2016 IPRD , SIENA, ITALY

23 Back up slides 05/10/2016 IPRD , SIENA, ITALY

24 The ATLAS experiment USA15 area On detector electronics
Mainly custom ASICs will be used – Radiation and magnetic fields Off detector electronics Placed in USA15 No radiation or magnetic field – commercial electronics will be used ATLAS detector 05/10/2016 IPRD , SIENA, ITALY

25 Radiation tolerant components
ROC Fabricated in IBM 130 nm CMOS technology Total area of 20 mm2 Was submitted for fabrication at 15/08/2016 VMM V2 available since 2014 and well tested V3 submitted and will be available at the end of this year" layout size 13.5×8.4 mm² transistor count ~ 5 million Supply voltage: 1.2 V Designed and fabricated using the 130nm 8‐metal CMOS technology from IBM The ASIC is packaged in a custom 21 x 21 mm² 400 ‐ pin BGA package 600mV baseline and +/‐ 150mV swing Power consumption 500 – 800 mW ROC ASIC TDS Power supply 1.5V 400 pin BGA Serial output 4.8 Gbps SLVS for differential and 1.5 V CMOS for single-ended Power consumption ~1 A VMM ASIC TDS ASIC (die) 05/10/2016 IPRD , SIENA, ITALY

26 Radiation tolerant components
FEAST ASIC Input voltage range 5 to 12V Minimum output voltage 0.6 V Continuous 4A load capability Very low output noise (Low Drop Out regulators will not be used) Adjustable switching frequency 1-3 MHz Radiation and magnetic tolerant: GBTX ASIC Is using the IBM/GlobalFoundries 130nm CMOS technology A serializer/deserializer Power 1.5V Power consumption is 2.2W (full operation) E-Links use Scalable Low-Voltage Signalling (SLVS) for 400mV (SLVS-400) GBTX ASIC VTRX optical transceiver (consists of 2 ASICS) The GigaBit TransImpendance Amplifier (GBTIA) Bit rate of 5 Gbps (min) Total jitter < 40 ps Supply voltage: 2.5 V Power consumption: 250 mW GigaBit Laser Diode (GBLD) Supply voltage: 2.5V Power consumption: 325mW 45.3 mm * 14:5 mm * 10mm (w * l * h) FEAST ASIC GBT-SCA ASIC Supply voltage: 1.5 V or 1.2 V Package Type: LFBGA 0.8 Pitch Pin count 196 Ball size 0.5mm VTRX vs SFP GBT-SCA ASIC VTTX 05/10/2016 IPRD , SIENA, ITALY

27 VMM Architecture Is designed to be used with the resistive strip micromegas and sTGC It integrates 64 channels, each providing: charge amplification Discrimination neighbor logic amplitude and timing measurements analog-to-digital conversions either direct output for trigger or multiplexed readout. 05/10/2016 IPRD , SIENA, ITALY

28 ROC Architecture Merges hits from up to eight VMMs, aggregates, adds headers, process and reformats the data generated by the VMM front-end chips Interfaces with up to Mbps or with up to Mbps For phase two (2 level trigger) ROC buffers the Level-0 accepted events until the arrival of a Level-1 trigger 05/10/2016 IPRD , SIENA, ITALY

29 ART Architecture 05/10/2016 IPRD , SIENA, ITALY

30 TDS Architecture Trigger Data Serialiser (TDS) ASICs are required to prepare trigger data for both sTGC pads and strips Two modes (selected by hardware pin) Strip-TDS Pad-TDS Performs pad-strip matching Serialize trigger data to the rim electronics (4.8 Gbps Bandwidth) 05/10/2016 IPRD , SIENA, ITALY

31 GBTX ASIC architecture
Radiation tolerant ASIC 1 E-Link is 3 differential pairs Clock (40, 80, 160 or 320 MHz) data-up (monitoring data – Level-1 data) data-down (configuration data) E-Links can be grouped in 5 independent banks that can support 40 80 Mbps Mbps Mbps Different E-Link configuration for each detector MMs: 8 FEs/L1DDC sTGC: 3 FEs/L1DDC Clock and data-down have the same phase Data-up are aligned to the GBTX clock Fiber side: 4.8 Gbps transmitting speed GBTX is configured by the Internal Control (IC) channel GBTX logic uses Triple Modular Redundancy (TMR) Figure taken from GBTX manual GBT Frame format 05/10/2016 IPRD , SIENA, ITALY

32 GBT-SCA Is used for monitoring and configuration purposes
Uses the SLVS standard 1 + 1 auxiliary 80 Mbps 8 x SPI master JTAG 16 x I2C 31 x Analog inputs 32 general purpose IOs 4 analogue outputs 05/10/2016 IPRD , SIENA, ITALY

33 Operation principle MMs and sTGC
Micromegas – channels Strip pitch: 450 μm for Large Module (LM), 425 μm for Small Module (SM) Readout Strips: 300 μm, Resistive Strips: 250 μm Data rates: LM – 7.99 Gbps/plane, SM – 4.39 Gbps/plane MM detector principle sTGC – channels sTGC wires/strips for tracking, strips/pads for trigger MM strips for tracking, first hit above threshold for trigger Wires: 50 μm, pitch 1.8 mm Strips: pitch 3.2 mm Data rates: Strips: LM – 1.77 Gbps/plane, SM – 1.14 Gbps/plane Pads & Wires: LM – 1.04 Gbps/plane, SM – 632 Mbps/plane sTGC detector principle 05/10/2016 IPRD , SIENA, ITALY

34 Level-0 & level-1 options
IDR single level: 1 MHz Level-0 accept with full detector readout, EFTrack, FTK++ and Event Filter IDR dual level: 1 MHz Level-0 accept, 400 kHz Level-1 accept (main rate reduction from L1Track), FTK++ and Event Filter “Low latency dual level”: 4 MHz Level-0 accept, 600 kHz Level-1 accept (main rate reduction from L1Track), FTK++ and Event Filter 05/10/2016 IPRD , SIENA, ITALY

35 Overall scheme Rim electronics – 10 boards 8 Routers 1 PAD trigger
1 RIM-GBT RIM-GBT Transmits configuration data and clock to SCA BC clock to FPGA Configuration data to FPGA Any additional data to FPGA Receives monitoring data from SCAs Data from the FPGA RIM boards 05/10/2016 IPRD , SIENA, ITALY

36 MMs detector MMs PCB layout Constructed MMs plane (Large Module)
05/10/2016 IPRD , SIENA, ITALY

37 RIM-L1DDC Transmits the TTC data to the trigger boards (Pad and Router) Receives monitoring and any additional data from the trigger boards Fully redundant board 2 GBTX ASICs 2 VTRX optical transceivers 18 miniSAS vertical connectors 8 + 8 for redundancy for Routers 1 + 1 for redundancy for Pads 2 voltage levels 1.5 V for GBTX ASICs 2.5 V for VTRX transceivers 4 FEASTs (2 for redundancy) GBTX standards SLVS for the Tx LVDS and SLVS for Rx Power consumption ~11 Watts 05/10/2016 IPRD , SIENA, ITALY

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