1. Status of DHP prototypes
PXD/SVD Workshop th September 2012
Tomasz Hemperek, Tetsuishi Kishishita, Hans Krüger, Mikhail Lemarenko, Manuel Koch , Leonard Germic

2. DHP Overview DHP 0.2 + Hybrid 5.0 DHPT 0.1 DHPT 0.2 DHPT 1.0 Planning
LVDS RX/TX
ADC
DHPT 1.0 Planning

3. One 1.6GB output link per chip
DHP
To SWITCHERS
10MHz read-out frequency
81.29Gbps
(320Mbps output data x 256 lines)
Per DHP chip:
8x8 bit wide data inputs
8x2 bit wide offset correction outputs
One 1.6GB output link per chip

4. DHP: Prototype & Tests Chips
DHP 0.1, IBM 90nm, March 2010, half size chip
DHP 0.2, IBM 90nm, July 2011, full size chip
Improved data processing & hit finder, new data format
CML driver with programmable pre-emphasis
Bias DACs & temperature sensor (U Barcelona)]
DHPT 0.1, TSMC 65nm, November 2011, test chip
Gbit TX (PLL, CML TX)
Memories + JTAG (radiation test)
DACs (UBarcelona)
DHPT 0.2, TSMC 65nm, April 2012, test chip
LVDS TX/RX
ADC (8 bit, 10MS)
TEMP Sensor (UBarcelona)
Planned: DHPT 1.0, TSMC 65nm, Q1 2013

5. DHP 0.2 (full size IBM 90nm) Summary
Verified Blocks
DHP Gbps,15m Infiniband
LVDS I/O
HSTL like Input
Slow control (JTAG)
Memory read/write
DCD interface
Switcher sequencer
DAC
Gbit link driver
Hybrid 5.0
Test system
See the talk of Florian Lüttike

6. DHPT 0.1 (prototype TSMC 65nm) Summary
DHPT 0.1, 20m of Infiniband of random data
100 mV
Memory SEU measurements conclusions
Memory type
Size
Mean time between SEU per one chip
Refresh rate
Mitigation
Raw data buffer
0.5 Mbit
~30 min
20 us
Pedestals
~15 min
Hamming code
Configuration Register
368 bit
490 day
~1day
Triple redundancy

7. DHPT 0.2 (prototype TSMC 65nm) Overview
LVDS TX/RX
ADC (8 bit, 10Msps)
TEMP Sensor (UBarceolona)
FE Pixels design (ATLAS)

8. DHPT 0.2 – LVDS RX/TX LVDS RX LVDS TX LVDS Reciver (1.8/2.5V)
M. Gronevald, T. Kishishita
LVDS Reciver (1.8/2.5V)
LVDS Transmitter (1.8/2.5V)
Level Shifters 1.2V<->1.8/2.5V
Custom IO (ARM compatible)

9. LVDS TX/RX Test Setup
T. Kishishita, L. Germic

10. DHPT 0.2 – LVDS TX/RX Both receiver and transmitter works as expected.
PRBS 320MHz - VDD 1.2V/1.8V
Both receiver and transmitter works as expected.

11. ADC chip on DHPT 0.2 4 x asynchronous 8bit ADC
4 x synchronous 8bit ADC
2 x TIA
Frequency divider+ serializer
LVDS TX
T. Kishishita, T. Hemperek

12. SAR ADC with Charge Redistribution - Overview
No distribution of fast clock needed - only sample signal!

13. Layout is not area optimized
Possible Layouts
Straight DAC
Folded DAC
30 um
40 um
DAC
DAC
70um
120 um
15 um
65um
Layout is not area optimized 13

14. ADC Testbench
T. Hemperek, T. Kishishita, M. Koch

15. DHPT 0.2 – ADC INL/DNL at 10MS/s
Single Ended Mode
Differential Mode
Power Consumption
Works up to 12.5MS/s

16. TIA
Range: 22uA
LSB: 86nA

17. (new feature requests till end 2012)
DHPT 1.0 (TSMC 65nm) Planning
Pin compatible to DHP 0.2 (still a bit smaller)
New programmable sequencer (gated mode included)
Improved programmable delay module for DCD signal sync.
Error flags included in frame header
Improved pedestal update (double buffer scheme)
New trigger mode for gated mode operation
... other
Submission in Q1 2013
(new feature requests till end 2012)

18. DHPT 1.0 Planner http://bit.ly/DHPT10Planner
Please send comments and feature requests to :

19. Questions?

20. Asynchronous SAR ADC

21. DHPT 0.2 – ADC INL/DNL at 12.5MS/s
Single Ended Mode
Differential Mode

22. Dynamic ADC measurements at 5MS/s
51 dB
Fundamental: 1MHz
SINAD: dB
ENOB:
THD: dB
We may be limited by generator or not!

23. Comparison DCD (180nm vs 65nm)
ADC bits 8
Pedestal Bits 2
Power per input (mW) ~3 ~1
Others
single DCD+DHP chip
No AmpLow