1. A Priori System-Level Interconnect Prediction The Road to Future Computer Systems
Dirk Stroobandt
Ghent University
Electronics and Information Systems Department
Presentation at Philips Natlab
November 28th, 2000

2. Dirk Stroobandt, talk at Philips Natlab
Outline
Part 1: A priori interconnect prediction methods
Why do we need a priori interconnect prediction?
Basic models
Rent’s rule and its applications
A priori wire length prediction
Multi-terminal nets
Recent evolutions
Part 2: A priori interconnect prediction applications
CAD (extrapolation, achievable routing, layer assignment)
Evaluation of new computer architectures
Circuit characterization and software/hardware codesign
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

3. Dirk Stroobandt, talk at Philips Natlab
Outline
Part 1: A priori interconnect prediction methods
Why do we need a priori interconnect prediction?
Basic models
Rent’s rule and its applications
A priori wire length prediction
Multi-terminal nets
Recent evolutions
Part 2: A priori interconnect prediction applications
CAD (extrapolation, achievable routing, layer assignment)
Evaluation of new computer architectures
Circuit characterization and software/hardware codesign
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

4. Why do we need a priori interconnect prediction?
Interconnect: importance of wires increases (they do not scale as components).
A priori: for future designs, very little is known. Roadmapping uses a priori estimation techniques.
To improve CAD tools for design layout generation.
CAD tools have to take into account: timing constraints, area constraints, performance, power dissipation…
All these constraints: wires should be as short as possible.
Estimation at early stage aids the CAD tools in finding a better solution through fewer design cycle iterations.
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

5. Why do we need a priori interconnect prediction?
To evaluate new computer architectures
To adhere to the increasing performance demands, new computer architectures are needed.
Each of them must be evaluated thoroughly.
A priori estimates immediately provide a ground for drawing preliminary conclusions.
Different architectures can be compared to each other.
Applications for evaluating three-dimensional (opto-electronic) architectures, FPGA’s, MCM’s,...
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

6. Components of the physical design step
circuit
architecture
Layout generation
layout
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

7. The three basic models Circuit model Model for the architecture
Pad
Channel
Manhattan grid
using Manhattan metric
Cell
Placement and routing model
Logic block
Net
Terminal / pin
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

8. Dirk Stroobandt, talk at Philips Natlab
Outline
Part 1: A priori interconnect prediction methods
Why do we need a priori interconnect prediction?
Basic models
Rent’s rule and its applications
A priori wire length prediction
Multi-terminal nets
Recent evolutions
Part 2: A priori interconnect prediction applications
CAD (extrapolation, achievable routing, layer assignment)
Evaluation of new computer architectures
Circuit characterization and software/hardware codesign
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

9. Dirk Stroobandt, talk at Philips Natlab
Rent’s rule
Rent’s rule was first described by [Landman and Russo, 1971]
For average number of terminals and blocks per module in a
partitioned design:
T = t B p
100 T
p = Rent exponent
t = average # term./block 10
Measure for the complexity
of the interconnection topology
Intrinsic Rent exponent p*
average
(simple) 0  p*  1 (complex)
Rent’s rule 1
Normal values: 0.5  p*  0.75 1 10
100
1000 B
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

10. Dirk Stroobandt, talk at Philips Natlab
Rent’s rule
Rent’s rule is a result of the self-similarity within circuits
Assumption: interconnection complexity is equal at all levels.
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

11. Rent’s rule If B cells are added, what is the increase T?
In the absence of any other information we guess T B B
Overestimate: many of T terminals connect to T terminals and so do not contribute to the total.
We introduce a factor p (p <1) which indicates how self connected the netlist is + placement optimization T
Statistically homogenous
system
Or, if B & T are small compared to B and T
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

12. Dirk Stroobandt, talk at Philips Natlab
Rent’s rule p
T = t B 1
1000 10
100 T B
Rent’s rule is experimentally
validated for a lot of real circuits
and for different partitioning
methodologies.
Distinguish between:
p* : intrinsic Rent exponent
p : Rent exponent for
a given placement
p’ : Rent exponent for
a given partitioning
average
Rent’s rule
Deviation for high B and T:
Rent’s region II
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

13. Use of Rent’s rule in CAD
Rent’s rule is very powerful as a measure of the complexity of the interconnection topology
Can aid in the partitioning process (prediction of partitioning result in cost function)
Benchmark generators are based on Rent’s rule
Is basis for a priori estimates in CAD
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

14. Dirk Stroobandt, talk at Philips Natlab
Outline
Part 1: A priori interconnect prediction methods
Why do we need a priori interconnect prediction?
Basic models
Rent’s rule and its applications
A priori wire length prediction
Multi-terminal nets
Recent evolutions
Part 2: A priori interconnect prediction applications
CAD (extrapolation, achievable routing, layer assignment)
Evaluation of new computer architectures
Circuit characterization and software/hardware codesign
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

15. Donath’s hierarchical placement model
1. Partition the circuit into 4 modules of equal size such that Rent’s rule applies (minimal number of pins).
2. Partition the Manhattan grid in 4 subgrids of equal size in a symmetrical way.
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

16. Donath’s hierarchical placement model
3. Each subcircuit (module) is mapped to a subgrid.
mapping
4. Repeat recursively until all logic blocks are assigned to exactly one grid cell in the Manhattan grid.
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

17. Donath’s length estimation model
At each level: Rent’s rule gives number of connections
number of terminals per module directly from Rent’s rule (partitioning based Rent exponent p’);
number of nets cut at level k (Nk) equals
where  depends on the total number of nets in the circuit and is bounded by 0.5 and 1.
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

18. Donath’s length estimation model
Length of the connections at level k ?
Adjacent (A-) combination
Diagonal (D-) combination  
Donath assumes: all connection source and destination cells are uniformly distributed over the grid.
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

19. Dirk Stroobandt, talk at Philips Natlab
Results Donath
Scaling of the average length L as a function of the number of logic blocks G : L G 5 10 15 20 25 30 1
100
103
106
105
104
107
p = 0.7
p = 0.5
p = 0.3
Similar to measurements on placed designs.
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

20. Dirk Stroobandt, talk at Philips Natlab
Results Donath
10000 L G 1 2 3 4 6 5 7 10
100
1000 8
experiment
theory
Theoretical average wire length too high by factor of 2
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

21. Including optimal placement model
Keep wire length scaling by hierarchical placement.
Improve on uniform probability for all connections at one level (not a good model for placement optimization).
Occupation probability favours short interconnections (for placement optimization) (darker)
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

22. Including optimal placement model
Wirelength distributions contain two parts:
site density function and probability distribution
all possibilities
requires enumeration
(use generating polynomials,
[Stroobandt & Van Marck, SLIP2000])
probability of occurrence
shorter wires more probable
[Stroobandt, VLSI Design vol. 10, 1999]
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

23. Wire length distribution
Local distributions at each level have similar shapes (self-similarity)  peak values scale.
Integral of local distributions equals number of connections.
Global distribution follows peaks.
For short lengths:
From this we can deduct that
Same result found as an approximation of a more exact equation in [Davis et al., 1998]
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

24. Occupation probability: results
Use probability on each hierarchical level (local distributions). 8
Occupation prob. 7
Donath 6
experiment 5 L 4 3 2 1 10
100
1000
10000 G
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

25. Occupation probability: results
Effect of the occupation probability: boosting the local wire length distributions (per level) for short wire lengths
percent of wires
Donath
Occupation prob.
100
global trend
global trend 10
per level
per level
total 1
total
0,1
0,01
10-3
10-4 1 10
100
1000
10000 1 10
100
1000
10000
Wire length
Wire length
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

26. Occupation probability: results
Effect of the occupation probability on the total distribution: more short wires = less long wires 
average
wire length
is shorter
percent wires
100
Donath 10
Occupation prob. 1
10-1
10-2
10-3
10-4
10-5 1 10
100
1000
10000
Wire length
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

27. Occupation probability: results
Percent wires 60
Donath 50
-8%
Occupation prob.
-23% 40
global trend 30
+10% 20
+6% 10 1 2 3 4 5 6 7 8 9 10
Wire length
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

28. Occupation probability: results
Number of wires
1000
Donath
Occupation prob.
100
measurement 10 1
0,1 1 10
100
Wire length
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

29. Dirk Stroobandt, talk at Philips Natlab
Outline
Part 1: A priori interconnect prediction methods
Why do we need a priori interconnect prediction?
Basic models
Rent’s rule and its applications
A priori wire length prediction
Multi-terminal nets
Recent evolutions
Part 2: A priori interconnect prediction applications
CAD (extrapolation, achievable routing, layer assignment)
Evaluation of new computer architectures
Circuit characterization and software/hardware codesign
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

30. Dirk Stroobandt, talk at Philips Natlab
Multi-terminal nets
Module at level k +1
Module at level k
Relation new terminals – nets cut:
Introduction of new parameter g
Cut at level k
Terminal at level k +1
Internal net (two new terminals)
Terminal at level k
External net (one new terminal)
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

31. Dirk Stroobandt, talk at Philips Natlab
Multi-terminal nets
Module at level k +1
Module at level k
Assume: internal and external net degree distributions known at level k: Wn(k) (normalized).
Recursive equations are found:
Cut at level k
Terminal at level k +1
Internal net (two new terminals)
Terminal at level k
External net (one new terminal)
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

32. Dirk Stroobandt, talk at Philips Natlab
Multi-terminal nets
Resulting net degree distribution matches experiments very well.
Analytical power law approximation possible.
Net degree distribution depends on two parameters:
Rent exponent p
New parameter g
For large designs: average net degree scales with 1/g
100000
Experimental measurement
Theoretical estimate
Approximation
10000
1000 d n
100 10 1 1 10
100 n
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

33. Length of multi-terminal nets
Level k +1
Difference between delay-related and routing-related applications:
Source-sink pairs
Assume A is source
A-B at level k
A-C and A-D at level k+1
Count as three connections
Entire Steiner tree lengths
Segments A-B, C-D and E-F
A-B and C-D at level k
E-F at level k+1
Add lengths to one net length A C E F B D
Level k
Net terminal
Steiner point
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

34. Dirk Stroobandt, talk at Philips Natlab
Multi-terminal nets
Steiner lengths versus source-sink pair
lengths
Donath versus occupation probability and
experiments for Steiner tree lengths
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

35. Dirk Stroobandt, talk at Philips Natlab
Outline
Part 1: A priori interconnect prediction methods
Why do we need a priori interconnect prediction?
Basic models
Rent’s rule and its applications
A priori wire length prediction
Multi-terminal nets
Recent evolutions
Part 2: A priori interconnect prediction applications
CAD (extrapolation, achievable routing, layer assignment)
Evaluation of new computer architectures
Circuit characterization and software/hardware codesign
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

36. Extension to three-dimensional grids
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

37. Dirk Stroobandt, talk at Philips Natlab
Anisotropic systems
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

38. Dirk Stroobandt, talk at Philips Natlab
Anisotropic systems
Not all dimensions are equal (e.g., optical links in 3rd D)
possibly larger latency of the optical link (compared to intra-chip connection);
influence of the spacing of the optical links across the area (detours may have to be made);
limitation of number of
optical layers
Introducing an optical cost
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

39. Dirk Stroobandt, talk at Philips Natlab
External nets
Importance of good wire length estimates for external nets during the placement process:
For highly pin-limited designs: placement will be in a ring-shaped fashion (along the border of the chip).
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

40. Wire lengths at system level
At system level: many long wires (peak in distribution).
How to model these?
Davis and Meindl ‘98:
estimation based on
Rent’s rule with the
floorplanning blocks
as logic blocks.
IMPORTANT!
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

41. Dirk Stroobandt, talk at Philips Natlab
Outline
Part 1: A priori interconnect prediction methods
Why do we need a priori interconnect prediction?
Basic models
Rent’s rule and its applications
A priori wire length prediction
Multi-terminal nets
Recent evolutions
Part 2: A priori interconnect prediction applications
CAD (extrapolation, achievable routing, layer assignment)
Evaluation of new computer architectures
Circuit characterization and software/hardware codesign
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

42. Improving CAD tools for design layout
Digital design is complex
Computer-aided
design (CAD)
More efficient layout generation requires good wire length estimates.
layer assignment in routing
effects of vias, blockages
congestion, ...
A priori estimates are rough but can already provide us with a lot of information.
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

43. Technology extrapolation
What is the most power-efficient noise management strategy?
Evaluates impact of
design technology
process technology
Evaluates impact on
achievable design
associated design problems
Questions to be addressed
Sets new requirements for CAD tools and methodologies
Roadmaps: familiar and influential example
How and when do L, SOI, SER, etc. matter?
Will layout tools need to perform process simulation to efficiently model cross-die and cross-wafer manufacturing variation?
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

44. Current extrapolation systems
Previous and ongoing efforts
ITRS Roadmaps
Tools: SUSPENS, GENESYS, RIPE, BACPAC, …
Numerous tools in industry
Use models for
delay
power
architecture
wirelength estimation
...
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

45. GTX: GSRC technology extrapolation system
GTX is set up as a framework for technology extrapolation
[Caldwell et al., DAC 2000]
Parameters (data)
Rules (models)
Rule chain (study)
Knowledge
Engine (derivation)
GUI (presentation)
Implementation
User inputs
Pre-packaged
GTX
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

46. Dirk Stroobandt, talk at Philips Natlab
GTX
Check it out at
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

47. Models of achievable routing
Required versus available resources
Required versus available resources
wirelength estimation models (Donath, …)
actual placement information
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

48. Models of achievable routing
limited by routing efficiency factor hr
Required versus available resources
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

49. Models of achievable routing
limited by power/ground (signal net fraction si)
Required versus available resources
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

50. Models of achievable routing
limited by via impact factor vi (ripple effect)
utilization factor Ui (available / supplied area)
Required versus available resources
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

51. Use of achievable routing models
Optimizing interconnect process parameters for future designs (number of layers, wire width and pitch per layer, ...)
With given layer characteristics: predict the number of layers needed
If number of layers fixed: oracle “(not) routable!”
(SUSPENS, GENESYS, RIPE, BACPAC, GTX)
Supplying objectives that guide layout tools to promising solutions (wire planning)
[Kahng, Mantik and Stroobandt, ISPD 2000]
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

52. Layer assignment in routing
DSM design routing tools have to account for
delay constraints
yield
power …
Conventional technique:
router assigns wires to layers
wire sizing, repeater insertion/sizing applied
More interesting approach:
wire sizing etc. used by router to assign wires [Kahng and Stroobandt, SLIP 2000]
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

53. Problem and Models
Find the optimal assignment of wires to wiring layers subject to delay constraints
and total repeater area constraints
Optimization objective: # of layers needed
Degrees of freedom (for each wire)
choice of layer parameters
wire width
number of repeaters
size of the repeaters
A priori estimation techniques make it useful for application both before / after placement
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

54. Dirk Stroobandt, talk at Philips Natlab
A Typical Example
Tier type 2
Tier type 1
Tier type 0
Delay (ps)
Wire width (mm)
Number of repeaters 2 2 4 2 4
Wirelength (mm)
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

55. Uniform Versus Non-uniform Stacks
Tier 2
Tier 1
Tier 0 10 9 8 7 6 5 4 3 2 1
Number of layers per tier type
8.0251
Total
7.1053
6.3134
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

56. Optimal Layer Stack Monotonic?
Tier 2
Tier 1
Tier 0 20 18 16 14 12 10 8 6 4 2
Number of layers per tier type
7.1285
7.0002
5.4426
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

57. Dirk Stroobandt, talk at Philips Natlab
Outline
Part 1: A priori interconnect prediction methods
Why do we need a priori interconnect prediction?
Basic models
Rent’s rule and its applications
A priori wire length prediction
Multi-terminal nets
Recent evolutions
Part 2: A priori interconnect prediction applications
CAD (extrapolation, achievable routing, layer assignment)
Evaluation of new computer architectures
Circuit characterization and software/hardware codesign
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

58. Opto-electronic FPGAs
Research question:
Is the use of massive optical interconnects at the logic level in general purpose electrical systems meaningful?
Answer depends on whether the properties of optical interconnections are comparable (or better) than those of the electrical ones they replace or complement
 Such a situation presents itself in electrical FPGAs
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

59. Dirk Stroobandt, talk at Philips Natlab
Area I/O in FPGAs
Future multi-FPGA emulators will face the following problems:
ASICs will keep growing: the need for multi-FPGA emulators will stay
FPGAs will have increasing numbers of CLBs
Complex designs have high Rent Exponents
 Pin and inter-FPGA interconnect limitations will keep increasing
Area I/O provides significant benefits in FPGAs*
*J. Depreitere, H. Van Marck, J. Van Campenhout, Microprocessors and Microsystems 21,
1998, pp
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

60. Dirk Stroobandt, talk at Philips Natlab
Why Area I/O in FPGAs ?
Design size (logic blocks)
Area I/O gain over Perimeter I/O (%)
(a) gain because wires do not have to be routed all the way to the perimeter
(b) gain when pin limitation problems are also considered
(a) gain because wires do not have to be routed all the way to the perimeter
Area I/O provides significant benefits in FPGAs*
*J. Depreitere, H. Van Marck, J. Van Campenhout, Microprocessors and Microsystems 21,
1998, pp
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

61. Dirk Stroobandt, talk at Philips Natlab
Why 3D FPGAs?
Different asymptotic average wire length*
Two-dimensional
Three-dimensional
Design size (logic blocks)
p =0.4
p =0.6
p =0.8
* J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, IEEE J. Sel. Topics in Quant. Electr. on Smart Phot. Comp., Interconnects, and Proc. (5)2, 1999, pp
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

62. Dirk Stroobandt, talk at Philips Natlab
Why 3D FPGAs ?
Wire length distribution differs significantly*
Distribution
Rent exponent r
Average wire length
* J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, IEEE J. Sel. Topics in Quant. Electr. on Smart Phot. Comp., Interconnects, and Proc. (5)2, 1999, pp
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

63. Dirk Stroobandt, talk at Philips Natlab
Effect of Anisotropy
Benefits are lower if anisotropy is higher*
Average wire length
Average wire length
7.5 5 7
Cost = 24
6.5 4 6
Cost = 16
5.5 3 5
4.5
Cost = 8 2 4
3.5 1
Cost = 1 3
2.5 1 5 10 15 20 25 1 2 4 6 8 10 12 14 16
Relative anisotropic cost
Number of layers (4096 gates)
* J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, IEEE J. Sel. Topics in Quant. Electr. on Smart Phot. Comp., Interconnects, and Proc. (5)2, 1999, pp
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

64. Dirk Stroobandt, talk at Philips Natlab
What Could It Look Like ?
A 3-D extension of the electrical on-chip interconnect fabric
offers a highly compact and densely interconnected multi-FPGA system
should provide an essentially 3-D routing environment, leading to shorter average wire lengths, hence faster systems
should provide an increased routability of complex designs
Other (hierarchical) interconnect schemes could be envisioned
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

65. Overview of the built system
Each FPGA has 128 optical receivers and 128 transmitters
System is designed for 80MHz (85 MHz measured)
FPGA chip contains about 165,000 transistors
About 1/3 of the FPGA chip is used for the optics
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

66. Dirk Stroobandt, talk at Philips Natlab
An optical prototype
0.6 mm chip
standard 145
pin PGA
socket
4 x 8 InP
detecor
arrays
4 x 8 LEDs
(VCSELs)
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

67. Dirk Stroobandt, talk at Philips Natlab
Outline
Part 1: A priori interconnect prediction methods
Why do we need a priori interconnect prediction?
Basic models
Rent’s rule and its applications
A priori wire length prediction
Multi-terminal nets
Recent evolutions
Part 2: A priori interconnect prediction applications
CAD (extrapolation, achievable routing, layer assignment)
Evaluation of new computer architectures
Circuit characterization and software/hardware codesign
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

68. Circuit characterization
We need parameters to classify circuits in classes and to optimize them.
Benchmark generation based on Rent’s rule.
Models beneficial for hardware/software partitioning?
Rent’s rule is a measure for the topological interconnection complexity of designs
A similar rule must exist for software (communication complexity)
We even hope to find a more general measure of “problem complexity”
Complexity models possibly help software/hardware partitioning.
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab

69. Dirk Stroobandt, talk at Philips Natlab
Conclusion
Wire length estimates are becoming more and more important.
A priori estimates can provide a lot of information at virtually no cost.
Methods are based on Rent’s rule.
Important for future research: how can we build a priori estimates into CAD layout tools?
More information at
Check out the International Workshop on System-level Interconnect Prediction (SLIP) at
November 28th, 2000
Dirk Stroobandt, talk at Philips Natlab