1. Date of download: 10/2/2017
Copyright © ASME. All rights reserved.
From: Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies
J. Electron. Packag. 2013;135(2): doi: /
Figure Legend:
Heat flux and area data from Refs. [6–8]. The vertical axis is the ratio of heat flux on individual functional unit to the average heat flux on the whole units or the die. The horizontal axis is the ratio of unit area to whole area. Also plotted are some of the data from the power scenarios used in the case studies of Sec. 4; the triangles on a curve are the data of the white-space-dominant scenario (rp,0 = 0.3, rp,k = 0 for k ≥ 1), and the squares on another curve are those of the self-similar scenario (rp,k = 0.3 for all k).

2. Date of download: 10/2/2017
Copyright © ASME. All rights reserved.
From: Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies
J. Electron. Packag. 2013;135(2): doi: /
Figure Legend:
Sketches of representative thermal environment for the die; (a) high-performance air-cooling, (b) conventional air-cooling, (c) high-performance liquid-cooling, (d) oil-cooling in IR measurement setup, and (e) a die in passively cooled casing

3. Date of download: 10/2/2017
Copyright © ASME. All rights reserved.
From: Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies
J. Electron. Packag. 2013;135(2): doi: /
Figure Legend:
Data of thermal resistance of air-cooled finned heat sinks collected from the literature and various commercial sources. The curve represents a correlation (5) which is used to form the parameters set for the case studies of Sec. 4. The line 0.1 K/W represents the target of research for finned heat sinks [31].

4. Date of download: 10/2/2017
Copyright © ASME. All rights reserved.
From: Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies
J. Electron. Packag. 2013;135(2): doi: /
Figure Legend:
Hierarchical layout of active and background cells on the die. The dimensions are used in the case studies reported in Sec. 4; the die footprint is 20 mm × 20 mm, the target spot of temperature calculation is at 13.3 mm from the corner of the die in both the horizontal and vertical directions.

5. Date of download: 10/2/2017
Copyright © ASME. All rights reserved.
From: Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies
J. Electron. Packag. 2013;135(2): doi: /
Figure Legend:
A three-layer model on which the heat conduction analysis is performed. On the die body (layer 1), the buried oxide (layer 2), and the wiring layer (layer 3) are stacked. The heat source plane is between the oxide and the wiring layers. The plan view (in the upper part of the figure) shows the footprint of the pilot heat source and a patch cell. The solution of this problem is used in several ways to construct the system of temperature calculations.

6. Date of download: 10/2/2017
Copyright © ASME. All rights reserved.
From: Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies
J. Electron. Packag. 2013;135(2): doi: /
Figure Legend:
Temperatures of the focal cell (θHS,k) and the background cell at the corner edge of the die (θmin), and their difference denoted as the temperature contrast (ΔθHS,k). The case is {“AC,” “Ref”} with the white-space-dominant scenario (rp,0 = 0.3, rp,k = 0 for k ≥ 1). The granularity level indexes are also shown. The horizontal axis is the normalized cell length.

7. Date of download: 10/2/2017
Copyright © ASME. All rights reserved.
From: Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies
J. Electron. Packag. 2013;135(2): doi: /
Figure Legend:
Heat flux on focal cell, and temperature contrast over the die in the case “AC”, plotted against the normalized cell length. (a) Heat fluxes for the white-space-dominant scenario (solid curve) and the self-similar scenario (broken curve). (b) Temperature contrasts for the two scenarios. Only in the white-space-dominant scenario the curves diverge in the range of fine granularities depending on the layer organization (Ref, Bulk, and No Wire).

8. Date of download: 10/2/2017
Copyright © ASME. All rights reserved.
From: Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies
J. Electron. Packag. 2013;135(2): doi: /
Figure Legend:
Heat flux on focal cell, and temperature contrast over the die for all cases of cooling condition under the white-space-dominant scenario. (a) Heat flux versus the normalized cell length. (b) Temperature contrast versus the normalized cell length.

9. Date of download: 10/2/2017
Copyright © ASME. All rights reserved.
From: Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies
J. Electron. Packag. 2013;135(2): doi: /
Figure Legend:
The ratio of heat flow from the focal cell to layer 3 (QU,k) to level-k excess heat (Qe,k) under the white-space-dominant scenario. The horizontal axis is the normalized cell length. (a) Case AC (high-performance air-cooling). (b) Case PC (a die in passively cooled casing).