1. Washington University
CS/CoE 536 Reconfigurable System On Chip Design Lecture 12 : Random Access Memory
Washington University
Fall 2002
John Lockwood
Copyright 2002

2. Dynamic RAM
DRAMs commonly used as main memory in processor based embedded systems
High capacity
Low cost
Many variations of DRAMs proposed
FPM DRAM: fast page mode DRAM
EDO DRAM: extended data out DRAM
SDRAM: Synchronous DRAM
RDRAM: rambus DRAM
Typically found off-chip
Due to process technology limitations
Slide From: Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

3. Basic DRAM Address bus multiplexed between row and column components
Row latched by strobing ras
Column latched by cas
Refresh circuitry can be external or internal
strobes consecutive memory address periodically causing memory content to be refreshed
Refresh circuitry disabled during read or write operation
Data
In Buffer
Out Buffer
rd/ wr
data
Row
Addr.
Buffer
Col
Addr
. Buffer
address
ras
cas
Bit storage array
Row Decoder
Col Decoder
Refresh
Circuit
cas,
ras, clock
Sense
Amplifiers
Slide From: Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

4. Fast Page Mode DRAM (FPM DRAM)
Each row of memory bit array is viewed as a page
Page contains multiple words
Individual words addressed by column address
Timing diagram:
Row (page) address sent
3 words read by sending column address for each
row
col
data
ras
cas
address
Slide From: Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

5. Extended data out DRAM (EDO DRAM)
Improvement of FPM DRAM
Extra latch before output buffer
allows strobing of cas before data read operation completed
Reduces read/write latency by additional cycle
row
col
data
Speedup through overlap
ras
cas
address
Slide From: Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

6. Synchronous DRAM (SDRAM)
SDRAM latches data on active edge of clock
Eliminates time to detect ras/cas and rd/wr signals
A counter incremented on edge of clock to access consecutive memory columns locations
clock
ras
cas
address
data
row
col
row
col
data
Slide From: Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

7. SDRAM Interface Specification
Off-Chip Synchronous Random
Access Memory (SDRAM)
.. Sarang ..
SDRAM_GRANT1
SDRAM
Interface
SDRAM_RQ
SDRAM_GRANT2
SDRAM_REQUEST_BUS[22:0]
SDRAM_DATA[63:0]

8. Detailed Operation of the Flow Buffer
Off-Chip Synchronous Random
Access Memory (SDRAM)
3: Packet Data stored in M[x]
2: packet from M[z]
Free List
Manager
5: z returned to the Free List
4: New memory pointer, y, provided from free list
Free.Ptr
4: M[z].data transmitted
Flow
Buffer
Packet Data p p
Packet Data
2: Queue Manager provides an address Memory pointer,
x = Flow[i].tail
Tail.Ptr
Head.Ptr
3: QM sets Flow[I].head = M[z].next
Flow#
Queue
Manager
1: New packet data arrives on Flow Number i
5: Queue Manager provided with new memory pointer, y.
Set Flow[i].tail = y
1: QM Decides it is time for a packet to depart. Reads Flow[i].head = z

9. Detailed Machine Problem 3 Structure
Off-Chip Synchronous Random
Access Memory (SDRAM)
Off-Chip Static Random
Access Memory (SRAM)
SDRAM
Controller
SRAM
Controller
Identify packets
Based on
SDRAM Free
List Manager
SDRAM
Free pointers
Content-
based
Match
(regex)
(MP2)
CAM-based
Firewall
(MP1 w/extra
entries & FlowID)
Flow
Buffer p p p p
Head
Pointers
Tail
Pointers
SRAM
Interface
Input
Traffic Data
From
Linecard 16
Output
Traffic
Data To
Linecard
or switch
Queue
Manager
(MP 3)
Scheduler
(RR, DRR, 3DQ)
Match
vector
Flow#
from CAM
Layered Protocol Wrappers
Firewall on a Chip
( Implemented on the RAD on the FPX, a VirtexE 2000 FPGA )