1. CS135602 Introduction to Information Engineering
Data Manipulation
2/19/2018
Che-Rung Lee
2018/2/19
CS Introduction to Information Engineering

2. CS135602 Introduction to Information Engineering
What is a computer?
Monitor, case, keyboard, mouse, speaker, scanner, webcam, printer, …
What’s inside?
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CS Introduction to Information Engineering

3. CS135602 Introduction to Information Engineering
Inside the case
CPU, motherboard, adaptors, hard disk, memory, CDROM, …
We are going to talk about those.
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CS Introduction to Information Engineering

4. Central Processing Unit (CPU)
An electronic circuit that can execute computer programs
Intel i7
AMD K10
IBM Cell
ARM Acorn
Sun SPARC
To understand CPU, we need to know what computer programs are.
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CS Introduction to Information Engineering

5. CS135602 Introduction to Information Engineering
Outline
Store program concept
Machine language
Program execution
Peripheral devices
Parallel architectures
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CS Introduction to Information Engineering

6. Stored Program Concept
"The final major step in the development of the general purpose electronic computer was the idea of a stored program..."  Brian Randell
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CS Introduction to Information Engineering

7. What’re the differences?
TV: you can watch different channels.
麵包機: you can make different food.
Swiss knife: you can use different tools
Computer: you can …
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CS Introduction to Information Engineering

8. Magic box You can add more functions to it. How?
Program is like data to be input to computers.
It can perform multiple functions at a time
We will talk about this in the OS lesson.

9. Stored-program concept
Program: a sequence of instructions
Stored-program concept: a program can be encoded as bit patterns and stored in main memory. From there, the CPU can extract the instructions and execute them.
Advantage: programmable
We can use a single machine to perform different functions.
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10. CS135602 Introduction to Information Engineering
Problems
How to convert instructions to operations?
This is like Harry Porter’s spell.
There should be a control unit.
To control which function to perform.
To control which data to be operated.
How can the control unit understand the instructions?
What function units should be included?
CD players, game console, calculators, …?
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11. Outline of the magic box
Processing unit
Storage unit for instructions and data
Control unit
Belt
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CS Introduction to Information Engineering

12. von Neumann architecture
general purpose electronic computer
Processing tools
Small but fast temporary storage
Large temporary storage for data and instructions
Figure 2.1 CPU and main memory connected via a bus
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13. What to do + Specified information
Machine Language
What to do +
Specified information
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CS Introduction to Information Engineering

14. CS135602 Introduction to Information Engineering
Computer programs
High Level Language Program
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
You are learning it in CS1355
Assembly Language Program
Compiler
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
You will learn it in CS2410
We are going to talk about those.
Machine Language Program
Assembler
Control Signal Specification
Machine Interpretation
ALUOP[0:3] <= InstReg[9:11] & MASK
This will be taught in CS4100
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CS Introduction to Information Engineering

15. CS135602 Introduction to Information Engineering
Example: a = b + c 1
1+2 3 2
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16. Represented by instructions
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17. CS135602 Introduction to Information Engineering
Instruction format
Store the data in register 5 to memory cell at address A7
Op-code: Specifies which operation to execute
Operand: Gives more detailed information about the operation
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18. CS135602 Introduction to Information Engineering
Another example
JUMP to instruction at address 58H if the content of register 2 is the same as that of register 0
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CS Introduction to Information Engineering

19. The instruction repertoire
Which instructions should be included?
For example, swapping v[k] and v[k+1]
swp 0($2), 4($2)
Create a new instruction, called swp, which swaps data in two memory addresses.
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
Using load and store instructions
Complex Instruction Set Computing (CISC)
Reduced Instruction Set Computing (RISC)
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CS Introduction to Information Engineering

20. CS135602 Introduction to Information Engineering
Instruction types
Data Transfer
Copy data between CPU and main memory
E.g., LOAD, STORE, device I/O,
Control
Direct the execution of the program
E.g., JUMP, BRANCH, JNE (conditional jump),
Arithmetic/Logic
Use existing data values to compute a new value
E.g., AND, OR, XOR, SHIFT, ROTATE, etc.
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21. CS135602 Introduction to Information Engineering
Instruction types
Data transfer
Data transfer
Arithmetic/Logic
Data transfer
Control
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22. CS135602 Introduction to Information Engineering
Program Execution
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23. Program execution cycle
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24. How to make a program “run”?
Figure The program from Figure 2.7 stored in main memory
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25. Instruction fetch
Figure Performing the fetch step of the machine cycle
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CS Introduction to Information Engineering

26. Processor Architecture
Memory
Function unit
Register 6C 1 1 2 2 6D 6E 3
Address bus 4 5 A0 15 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4 56 A5 A6 30
Instruction register 6E A7 C0 A8 00 A9
Controller

27. Fetch Instruction 1 6C 1 1 2 2 6D 6E 3 Address bus 4 5 A0 15 6 6C A1
Processor
Memory
Function unit
Register
Decode 6C 1 1 2 2 6D 6E 3
Address bus 4 5 A0 A0 15 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4
156C 56 A5 A0 A2 A6 30
Instruction register 6E A7
156C C0 A8 00 A9
Controller

28. Decode Instruction 1 6C 1 1 6D 2 2 6E 3 Address bus 4 5 A0 15 6 6C A1
Processor
Memory
Function unit
Register 6C 1 1 6D 2 2 6E 3
Control
signal
Address bus 4 5 A0 15 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4 56 A5
Decode A2 A6 30
Instruction register 6E A7
156C C0 A8 00 A9
Controller

29. Execute Instruction 1 6C 1 1 6D 2 2 6E 3 Address bus 4 1 5 A0 15 6 6C
Processor
Memory
Function unit
Register 6C 1 1 6D 2 2 6E 3
Address bus 4 1 5 6C A0 15 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4 1 56 A5
Decode A2 A6 30
Instruction register 6E A7
156C C0 A8 00 A9
Controller

30. Fetch Instruction 2 6C 1 1 6D 2 2 6E 3 Address bus 4 1 5 A0 15 6 6C A1
Processor
Memory
Function unit
Register 6C 1 1 6D 2 2 6E 3
Address bus 4 1 5 A2 A0 15 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4
166D 56 A5 A2 A4 A6 30
Instruction register 6E A7
166D C0 A8 00 A9
Controller

31. Decode Instruction 2 6C 1 1 6D 2 2 6E 3 Address bus 4 1 5 A0 15 6 6C
Processor
Memory
Function unit
Register 6C 1 1 6D 2 2 6E 3
Address bus 4 1 5 A0 15 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4 56 A5
Decode A4 A6 30
Instruction register 6E A7
166D C0 A8 00 A9
Controller

32. Execute Instruction 2 6C 1 1 6D 2 2 6E 3 Address bus 4 1 5 A0 2 15 6
Processor
Memory
Function unit
Register 6C 1 1 6D 2 2 6E 3
Address bus 4 1 5 6D A0 2 15 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4 2 56 A5
Decode A4 A6 30
Instruction register 6E A7
166D C0 A8 00 A9
Controller

33. Fetch Instruction 3 6C 1 1 2 6D 2 6E 3 Address bus 4 1 5 A0 15 2 6 6C
Processor
Memory
Function unit
Register 6C 1 1 2 6D 2 6E 3
Address bus 4 1 5 A4 A0 15 2 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4
5056 56 A5 A4 A6 A6 30
Instruction register 6E A7
5056 C0 A8 00 A9
Controller

34. Decode Instruction 3 6C 1 1 6D 2 2 6E 3 Address bus 4 1 5 A0 15 2 6 6C
Processor
Memory
Function unit
Register 6C 1 1 6D 2 2 6E 3
Address bus 4 1 5 A0 15 2 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4 56 A5
Decode A6 A6 30
Instruction register 6E A7
5056 C0 A8 00 A9
Controller

35. Execute Instruction 3 3 6C 1 1 Adder 2 6D 2 6E 3 Address bus 4 1 5 A0
Processor
Memory
Function unit
Register 3 6C 1 1
Adder 2 6D 2 6E 3
Address bus 4 1 5 A0 15 2 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4 56 A5
Decode A6 A6 30
Instruction register 6E A7
5056 C0 A8 00 A9
Controller

36. Fetch Instruction 4 3 6C 1 1 6D 2 2 6E 3 Address bus 4 1 5 A0 15 2 6
Processor
Memory
Function unit
Register 3 6C 1 1 6D 2 2 6E 3
Address bus 4 1 5 A6 A0 15 2 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4
306E 56 A5 A6 A8 A6 30
Instruction register 6E A7
306E C0 A8 00 A9
Controller

37. Decode Instruction 4 3 6C 1 1 2 2 6D 6E 3 Address bus 4 1 5 A0 15 2 6
Processor
Memory
Function unit
Register 3 6C 1 1 2 2 6D 6E 3
Address bus 4 1 5 A0 15 2 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4 56 A5
Decode A8 A6 30
Instruction register 6E A7
306E C0 A8 00 A9
Controller

38. Execute Instruction 4 3 6C 1 1 2 6D 2 3 6E 3 Address bus 4 1 5 A0 15 2
Processor
Memory
Function unit
Register 3 6C 1 1 2 6D 2 3 6E 3
Address bus 4 1 5 6E A0 15 2 6 6C A1 16 A2 F A3
Data bus 6D
Program counter 50 A4 3 56 A5
Decode A8 A6 30
Instruction register 6E A7
306E C0 A8 00 A9
Controller

39. CS135602 Introduction to Information Engineering
Instruction decode
How to map opcodes to desired circuits on a CPU?
For example:
00b: add
01b: or
10b: jump
11b: and
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40. Interpretation of operand
The interpretation of operand depends on the op-code
Opcode
Operand
Description 1
4 A 3
Load the content at address A3 to register 4 2
Load value “A3” to register 4 4
0 A 3
Move the content of register A to register 3
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41. Instruction execution
Uses logic circuits
Data transfer: load, store, …
Logic circuit for registers (Ex: flip-flops)
Control: jump, jump-equal, …
Change the value of program counter (PC)
Comparison logic circuit
Arithmetic/Logic: add, and, shift, …
Again, logic circuits (adder, as we have seen.)
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42. CS135602 Introduction to Information Engineering
Flip-flops
A logic circuit that can store one bit.
Upper input is used to set its stored value to 1
Lower input is used to set its stored value to 0
While both input lines are 0, the most recently stored value is preserved
Initially, both inputs and output are 0
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43. CS135602 Introduction to Information Engineering
Flip-flops: set value 1 1
The input signal
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44. CS135602 Introduction to Information Engineering
Flip-flops: set value 0
Input (1,1) is undefined
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45. CS135602 Introduction to Information Engineering
Example of jump
JUMP to instruction at address 58H if the content of register 2 is the same as that of register 0
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46. CS135602 Introduction to Information Engineering
Example of jump-equal
B258: JUMP to instruction at address 58H if the content of register 2 is the same as that of register 0
Input
XOR 1
In case you forgot what XOR is
Register 0
Register 2 :
XOR OR
NOT
Program
counter
set
58H=
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47. Arithmetic/Logic Operations
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48. Arithmetic/Logic operations
Arithmetic: add, subtract, multiply, divide
Precise action depends on how the values are encoded (two’s complement vs. floating-point)
Shift
circular shift (Rotate), logical shift, arithmetic shift
Logic: AND, OR, XOR, NOT
Masking
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49. CS135602 Introduction to Information Engineering
One bit full adder
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50. CS135602 Introduction to Information Engineering
4 bit parallel adder
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51. CS135602 Introduction to Information Engineering
Rotate operation
Figure Rotating the bit pattern 65 (hexadecimal) one bit to the right
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CS Introduction to Information Engineering

52. CS135602 Introduction to Information Engineering
Shift operation
Circular shift (rotation)
Logical shift
Filling the hole with bit 0
Original: b  5d
After 1 left shifting: b  10d
After 2 left shifting: b  20d
Arithmetic shift
Shifts that leaves the sign bit unchanged
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CS Introduction to Information Engineering

53. CS135602 Introduction to Information Engineering
Arithmetic shift
The two’s complement of b (10d) is b (-10d)
Want to use right shift to perform -10/2=-5,
b >> 1 = b = ?
We want the first bit to be 1. ( b =-5)
Arithmetic shift
Copy the first bit 1 b
_ b
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54. CS135602 Introduction to Information Engineering
Masking
AND, OR, XOR can be used for masking
Example: bit operations on b
Set the 4th bit to 0
Set the 3rd bit to 1
Invert the 3rd and the 4th bit
AND
Mask OR
XOR
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55. Examples of using masks
Ex1: the floating point described in chap 1,
Design masks to retrieve sign, exponent, and mantissa.
Design a mask to set sign.
Ex2: The ASCII code described in chap 1,
Design a mask to convert capital letters to small letters or vice versa A a B b C c D d E
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56. Put everything togetherZ N
register
Memory PC IR
Controller
ALU
clock
Control
signal
Datapath
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57. Exercises Suppose PC=B0
What is in register 3 after the first instruction?
What is the memory cell B8 when the program halts?
Address
Contents B0 13 B1 B8 B2 A3 B3 02 B4 33 B5 B6 C0 B7 00 0F

58. Exercises
Design a mask to isolate the middle four bits of a byte (set others = 0).
Encode each of the following commands
ROTATE the contents of register 7 to the right 5 bit positions
ADD the contents of registers 5 and 6 as thought they were values in floating-point notation and leave the result in register 4
AND the contents of registers 5 and 6, leaving the result in register 4.

59. CS135602 Introduction to Information Engineering
Peripheral Devices
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60. Connecting to other devices
Outside the case
Port: The point at which a device connects to a computer
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61. CS135602 Introduction to Information Engineering
Inside the case
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62. CS135602 Introduction to Information Engineering
Device controller
An intermediary apparatus that handles communication between the computer (CPU/memory) and a device.
Two types of controllers
Specialized controllers
Network card, graphics card, …
General purpose controllers
USB, FireWire, …
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63. CS135602 Introduction to Information Engineering
Device addressing
Memory-mapped I/O:
CPU communicates with peripheral devices as though they were memory cells
Use load and store to access device data
Dedicated I/O instructions for devices
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64. Direct memory access (DMA)
DMA is a mechanism for devices to access memory without occupying CPU.
At the same time, CPU can execute “other process” until the I/O is finished.
Better system throughput
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65. CS135602 Introduction to Information Engineering
Communication type
Parallel Communication:
Several communication paths transfer bits simultaneously.
Printer, computer bus
Serial Communication:
Bits are transferred one after the other over a single communication path.
USB, FireWire
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66. Exercises
Suppose the machine use memory I/O and the memory address B5 is the location within the printer port to which data to be printed. If register 7 contains the ASCII code for the letter A, what instruction can make letter A to be printed?
If a printer can only print 128 characters per second, and has local buffer of 256KB, how fast the data rate (bps) can be?

67. Parallel Architectures
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68. CS135602 Introduction to Information Engineering
Pipeline
Program execution is divided into three stages: fetch, decode, execute
Suppose each stage takes 1 clock cycle.
How many clock cycles are needed to execute 1 instruction?
How many clock cycles are needed to execute 50 instructions?
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69. CS135602 Introduction to Information Engineering
Pipeline
Since the hardware used in each stage is separated, CPU can overlap the stages
The more stages, the better throughput ?
Throughput = # executed instructions/time
Pentium 4 had a 35-stage pipeline.
Clk 1 Clk2 Clk 3 Clk 4 Clk 5 Clk 6 Clk 7 Clk8 Clk 9
Fetch
Inst 1
Inst 2
Inst 3
Inst 4
Inst 5
Inst 6
Inst 7
Inst 8
Inst 9 …
Decode
Execute
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CS Introduction to Information Engineering

70. Pamphlet assembling example
Suppose there are 100 pamphlets to be assembled, each of which has 6 pages.
The printouts of each page are put into a pile.
Assembling one page takes 1 second.
Page 1, …page 6 need be assembled in order.
Assembling one pamphlet takes 6 seconds.
How fast can it be done by one person?
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
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71. CS135602 Introduction to Information Engineering
How fast can it be done by two persons?
How fast can it be done by three persons?
Analogy
Number of persons  number of stages
Number of seconds number of clock cycles
How fast can it be done by 7 persons?
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
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CS Introduction to Information Engineering

72. Clock cycle/clock rate
The basic time unit of a CPU
For example, a 2GHz CPU has clock cycle 1/2G = 5×10-10 second.
2GHz is the “clock rate” of a CPU.
Every operation in CPU takes the time that is a multiple of the clock cycle.
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CS Introduction to Information Engineering

73. Parallel architectures
Bit-level parallelism:
1 bit adder vs. 4 bit adder
Instruction-level parallelism
Pipeline: overlap instruction execution stages
IO/computation parallelism
DMA: overlap communication/computation
Multiprocessor parallelization
Cluster, multi-core processors, GPU
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74. CS135602 Introduction to Information Engineering
Flynn's taxonomy
Based on the number of concurrent instruction and data streams available in the architecture (Michael J. Flynn, 1966)
SISD (Single-instruction, single-data stream)
No parallel processing
MIMD (Multiple-instruction, multiple data stream)
Different programs, different data
SIMD: (Single instruction, multiple data stream)
Same program, different data
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75. CS135602 Introduction to Information Engineering
SIMD example
SISD for-loop
for(i=0;i<5;i++) A[i]=B[i]+C[i];
SIMD expansion
CPU 1: A[0]=B[0]+C[0];
CPU 2: A[1]=B[1]+C[1];
CPU 3: A[2]=B[2]+C[2];
CPU 4: A[3]=B[3]+C[3];
CPU 5: A[4]=B[4]+C[4];
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76. CS135602 Introduction to Information Engineering
By memory location
Distributed memory system
Multiple processors that communicate through a computer network.
Shared memory system
Multiple processors that communicate through a shared memory space.
Hybrid system
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77. Speedup
Amdahl’s law
Suppose there are f% of tasks cannot be parallelized, the best speedup by n processors is

78. CS135602 Introduction to Information Engineering
Supercomputers
Hundred thousands of processors interconnected via special designed network
Top1: Roadrunner
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79. CS135602 Introduction to Information Engineering
Multi-core processor
A processor composed of two or more independent cores (or CPUs).
Advantages
Performance improvement
Low power consumption
Disadvantages
Operating system support
Software support
We will talk those problems later
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80. Graphics processing unit (GPU)
A specialized processor designed for 3D graphics rendering
Modern GPU has over thousand cores, which can be used for general purpose computation
CPU
GPU
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81. Exercises
Suppose instructions can be fully overlapped in a 3 stages pipeline CPU, and each stage takes 3 clock cycles, how many clock cycles are needed to execute 500 instructions? How if there are 5 stages?
What is the best speedup for 10 processors if there are 20% of tasks can be parallelized? How about 60%?

82. CS135602 Introduction to Information Engineering
Related courses
Store program concept, peripheral devices
計算機結構，硬體實驗，微算機系統，邏輯設計，嵌入式系統概論
Parallel Architectures
References
(supercomputer)
Textbook chap 2
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CS Introduction to Information Engineering

83. Opcode Operand Description1
RXY
LOAD the register R with the bit pattern found in the memory cell whose address is XY. Example: I4A3 would cause the contents of the memory cell located at address A3 to be placed in register 4. 2
LOAD the register R with the bit pattern XY. Example: 20A3 would cause the value A3 to be placed in register 0. 3
RST
STORE the bit pattern found in register R in the memory cell whose address is XY. Example: 35B1 would cause the contents of register 5 to be placed in the memory cell whose address is B1. 4
ORS
MOVE the bit pattern found in register R to register S. Example: 40A4 would cause the contents of register A to be copied into register 4. 5
ADD the bit patterns in registers S and T as though they were two's complement representations and leave the result in register R. Example: 5726 would cause the binary values in registers 2 and 6 to be added and the sum placed in register 7.

84. Opcode Operand Description6
RST
ADD the bit patterns in registers S and T as though they represented values in floating point notation and leave the floating-point result in register R.
Example: 634E would cause the values in registers 4 and E to be added as floating-point values and the result to be placed in register 3. 7
OR the bit patterns in registers S and T and place the result in register R.
Example: 7CB4 would cause the result of ORing the contents of registers Band 4 to be placed in register C. 8
AND the bit patterns in registers S and T and place the result in register R.
Example: 8045 would cause the result of ANDing the contents of registers 4 and 5 to be placed in register 0. 9
EXCLUSIVE OR the bit patterns in registers Sand T and place the result in register R. Example: 95F3 would cause the result of EXCLUSIVE ORing the contents of registers F and 3 to be placed in register 5

85. Opcode Operand Description
R0X
ROTATE the bit pattern in register R one bit to the right X times. Each time place the bit that started at the low-order end at the high-order end. Example: A403 would cause the contents of register 4 to be rotated 3 bits to the right in a circular fashion. B
RXY
JUMP to the instruction located in the memory cell at address XY if the bit pattern in register R is equal to the bit pattern in register number 0. Otherwise, continue with the normal sequence of execution. (The jump is implemented by copying XY into the PC during the execute phase.) Example: B43C would first compare the contents of register 4 with the contents of register 0. If the two were equal, the pattern 3C would be placed in the program counter so that the next instruction executed would be the one located at that memory address. Otherwise, nothing would be done and program execution would continue in its normal sequence. C
000
HALT execution. Example: C000 would cause program execution to stop.