1. Automatic Analog Integrated Circuits Layout Generator
9th Annual “HUMIES” Awards for Human-Competitive Results
Genetic and Evolutionary Computation Conference (GECCO), 2012
Automatic Analog Integrated Circuits Layout Generator
Ricardo Martins, Nuno Lourenço, Nuno Horta
IT / Instituto Superior Técnico, Lisbon, Portugal

2. 9th Annual “HUMIES” Awards, GECCO
OUTLINE
Introduction and Motivation
A brief description of the submitted Work
R. Martins, N. Lourenço, N. Horta, “LAYGEN II – Automatic Analog ICs Layout Generator based on a Template Approach”, Genetic and Evolutionary Computation Conference (GECCO) 2012, July 2012, Philadelphia, USA.
R. Martins, "LAYGEN II – Automatic Layout Generation of Analog ICs based on Template Descriptions and Evolutionary Computation", Master thesis in Electrical Engineering, May 2012, IST, Lisbon, Portugal. (To be published by Springer)
Why our result is “Human-Competitive”
Why our result is the “best” entry
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

3. [J. Goes et al, UNINOVA/CTS, 2011] 9th Annual “HUMIES” Awards, GECCO
Integrated Circuit
Layout generation consists of creating the geometrical layout of the block under design at the lowest level in the design hierarchy, or place and route the layouts of the sub-blocks at higher levels. In the presented design flow, it is important to notice the presence of a detailed verification step over the extraction of the layout. In order to ascend to higher hierarchical levels is necessary that no potential problems are detected at the lowest levels and the layout meet the target requirements. When the topmost level verification is complete, the system is designed.
[J. Goes et al, UNINOVA/CTS, 2011]
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

4. Why Analog IC Design Automation?
In today’s ASICs, analog circuits establish the LINK between digital circuitry and the continuous-valued external world.
COMPUTER-AIDED DESIGN TOOLS
Digital:
Auto Synthesis;
Auto Layout;
Highly Reusable IP.
Analog:
Limited Auto Synthesis;
Limited Auto Layout;
Hardly Reusable IP.
[Rob A. Rutenbar, 2010]
While generally all the processing is done by digital circuitry, Analog circuits ARE NECESSARY to interface with the real world! And ocupy only a small fraction of the IC, but the design effort is much superior when compared to the digital design.
This is due to the lack of CAD tools that support the analog design. While in digital…
In the industry, analog IC layout design is supported by circuit simulators, layout editors and verification tools, which maintain the design cycles long
On the other hand, analog blocks constitute only a small fraction of the components on mixed-signal ICs and SoC designs, being essentially the link between digital circuitry and the continuous-valued external world, so are also integrated on the same die [3]. However, the development time of analog blocks is much higher when compared to the development time of the digital blocks. The two main reasons identified for the larger development cycle of analog blocks are the lack of effective computer-aided-design (CAD) tools for EDA, since analog design is less systematic, more knowledge-intensive and more heuristic in nature than the digital counterpart; and that analog circuits are being integrated using technologies optimized for digital circuits. For this reason, given the rampant growth of AMS systems, the economic pressure for high-quality yet cheap electronic products and time-to-market constraints, there is an urgent need for CAD tools that increase the analog design productivity and improve the quality of resulting ICs [4].
Urgent need for CAD tools that Increase analog designers’ productivity and Reduce development cycles.
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

5. Analog IC Layout Generation Task
DIFICULTIES
Due to the lack of automation, designers keep exploring the solution space MANUALLY using traditional layout editors;
Iterative and ERROR-PRONE task;
Demanding design rules of the NANOMETER technologies;
NON-REUSABLE nature of analog IC layout.
While devices can be instatiated from the libraries, all the wires required for the interconnections are drawn manually!
[CADENCE® Virtuoso Layout Editor]
Analog layout design is many technology nodes behind leading-edge digital.
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

6. Automatic Layout Synthesis using LAYGEN II
The designer avoids time-consuming traditional editors.
ANALOG DESIGNER
AUTOMATICALLY GENERATED LAYOUT
Emphasis to the reusability of expert knowledge and efficiency on retargeting operations;
All the automatically generated layouts are validated in CALIBRE®, a main reference in the IC design industry.
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

7. Why our result is “Human-Competitive”
(D) The result is publishable in its own right as a new scientific result.
Automatically Generated by LAYGEN II
[R. Martins et al, “Multi-Objective Multi-Constraint Routing of Analog ICs using a modified NSGA-II Approach”, SMACD 2012]
Handmade Layout
[J. Goes et al, “A 1.2V 300µW second-order switched-capacitor Δ∑ modulator”,´ESSCIRC 2011]
Handmade layout by an experienced designer
The International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
Avoids traditional layout editors!
Automatically generated layouts compete with human-created solutions in terms of: ROBUSTNESS, QUALITY and GENERATION TIME.
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

8. Why our result is “Human-Competitive”
(D) The result is publishable in its own right as a new scientific result.
SIMULATIONS
SCHEMATIC
(Without non-idealities of layout)
Post-Layout:
HANDMADE
LAYGEN II
Results were validated in calibre DRC and LVS
Automatically generated results sent for fabrication for the ultimate ON-DIE comparison with human-created solutions.
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

9. Why our result is “Human-Competitive”
(E) The result is equal to or better than the most recent human-created solution to a long-standing problem.
Our approach beats the existing state-of-the-art solutions by:
Implementing a technology and specification independent approach;
General for any circuit class;
Fast, flexible and robust generation based on evolutionary optimization kernel;
Designer could easily take hours in the traditional layout editors;
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

10. Why our result is “Human-Competitive”
(E) The result is equal to or better than the most recent human-created solution to a long-standing problem.
Efficiency on retargeting for different SPECIFICATIONS
Design 1
Design 2
Design 3
Area [µm²]
-a0 [dB]
Design 1
Design 2
Design 3
Designer could easily take hours in the traditional layout editors;
SETUP TIME + AUTOMATIC GENERATION < 10 MINUTES
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

11. Why our result is “Human-Competitive”
(E) The result is equal to or better than the most recent human-created solution to a long-standing problem.
Efficiency on retargeting for different TECHNOLOGIES
AMS 350 nanometers
UMC 130 nanometers
The presented approach produces layout solutions and performs redesign operations in few minutes, for cases where a designer can easily take hours using the traditional layout editors, since in the handmade design the solution is iteratively changed until no design rule is violated.
DIFFERENT TECHNOLOGIES = DIFFERENT DESIGN RULES
SETUP TIME + AUTOMATIC GENERATION < 10 MINUTES
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

12. Why our result is “Human-Competitive”
(G) The result solves a problem of indisputable difficulty in its field.
The solution space grows rampantly with the number of devices to place and wires to route, always considering technologies with strict design rules and several layers, which all together lead to a huge problem;
The designer can easily take HOURS to explore partially the solution space;
Retargeting operations performed handmade usually lead to partial or COMPLETE LOSS of the previous work.
(G), since from an industrial point of view the application of electronic design automation tools in analog layout synthesis is still far away from being a reality. The analog layout problem includes both placement and routing tasks, which means generating the representations for each circuit structure in a technological process with several layers. Moreover, the solutions must comply with the strict technological design rules, which all together lead to huge decision and solution space.
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

13. Why our result is the “best” entry
We solve real problems of a $300 billion industry;
The approach deals with a problem of indisputable difficulty, that is still solved manually by designers in the industry, in a time consuming and error-prone process;
LAYGEN II considers challenging nanometer technologies. We have published results and sent for fabrication for a 130 nanometer design process.
“In October 2010, TI acquired a 200mm wafer fab in Chengdu, China.”
Technology node:
TI’s 350 nanometer LBC5 Power BiCMOS
(1) The approach solves a problem of indisputable difficulty for the ever-increasing integrated circuits industry and considering challenging technologies.
we are currently moving to 65 nanometers design processes
[Texas Instruments]
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA

14. 9th Annual “HUMIES” Awards, GECCO
THANK YOU
9th Annual “HUMIES” Awards, GECCO
| July 07-12, 2012, Philadelphia, USA