1. ARM AT91EB55 Development Board & ATMEL AT91M55800A ARM7TDMI
CMPE 450/490
ARM AT91EB55 Development Board &
ATMEL AT91M55800A ARM7TDMI
©2010 Elliott, Durdle, Minderman
Portions courtesy of ARM, Atmel, Greenhill

2. Overview The AT91EB55 board contains:
An ATMEL AT91M55800A ARM7TDMI microcontroller
2M bytes of 16-bit Flash
of which 1 MB is available for user software
256K byte of 16-bit SRAM
upgradable to 1 MB
4M bytes of Serial Data Flash
upgradeable to 16 MB
Two serial ports
Eight LEDs
Four user-defined push buttons
Reset push button
20-pin JTAG interface connector
3 x 32 pin I/O expansion connector
2 x 32 pin EBI expansion connector

3. The AT91EB55 Board Layout

4. AT91EB55 Block Diagram
Real-time Clock, Advanced Power Management Controller, Watchdog Timer, Interrupt Controller, Clock Generator, Serial Ports, DAC, ADC, Serial Peripheral Interface, Timer Counters,
Parallel I/O Controller, External Bus Interdface

5. Testing the AT91EB55 Evaluation Board
To test the AT91EB55 Evaluation board, hold down the SW1 button and power up the board or generate a reset and wait for the light sequence on each LED to complete.
All the LEDs light once and the D1 LED remains lit.
Release the SW1 button.
The LEDs D1 to D7 light up in sequential order.
If an error is detected, all the LEDs will light up twice.
The LEDs represent the following devices:
D1 for the internal SRAM
D2 for the external SRAM
D3 for the external Flash
D4 reserved
D5 for the SPI data flash
D6 reserved
D7 for the USART
D8 for the ADC and DAC

6. On Board Software
The 2MB AT49BV162A Flash ROM contains with the following software.
The Boot Software Program (boot)
The Functional Test Software (FTS)
The Angel Debug Monitor
A Default User Boot with a Default Application
Only the lowest eight 8-Kbyte sectors are used.
The remaining sectors are user-definable and can be programmed using one of the Flash downloader solutions offered in the AT91 library
The boot and FTS and are in sectors 0 and 1 of the Flash when delivered
These sectors are not locked for an easy on-board upgrade.
The user must avoid overwriting this sector.

7. The Boot Program The Boot Software Program configures the AT91M55800A
It thus controls the memory and other board devices.
The Boot Program is started at reset if JP1 is in the STD position.
If JP1 is in the USER position
the AT91M55800A boots from address 0x in the Flash,
which must have a user-defined boot.
The Boot Program
Initializes the master clock frequency at 32 MHz
Configures the EBI
Executes the REMAP
Checks the state of the buttons
As long as the SW1 button is pressed, all the LEDs light together
The D1 LED remains lit until SW1 is released
The Functional Test Software (FTS) is then started
When the SW4 button is pressed the shutdown function from AT91M55800A is activated.
When no buttons are pressed, branch to address 0x
The Angel Debug Monitor starts from this address by recopying itself in external SRAM

8. Default Memory Map
Part Name
Start Address
End Address
Size
Device U1 0x
0x011FFFFF
2-Mbyte
Flash ROM
U2-U3 0x
0x0203FFFF
256-Kbyte
SRAM
The Boot Program and FTS and are in sectors 0 and 1 of the Flash device
Sectors 3 to 7 support the Angel Debug Monitor
Sector 24 at address 0x must be programmed with a boot sequence to be debugged.
This sector can be mapped at address 0x (or 0x0 after a reset) when the jumper JP1 is in the USER position.

9. Default Memory Map (continued)

10. The Angel Debug Monitor
The Angel Debug Monitor is located in the Flash ROM
from 0x up to 0x0100FFFF
The boot program starts it if no button is pressed.
When Angel starts, it recopies itself in SRAM in order to run faster.
The SRAM used by Angel is from 0x to 0x0203FFFF, i.e., the highest half part of the SRAM.
The Angel on the AT91EB55 can be upgraded regardless of the version programmed on it.
Note: If the debugger is started through ICE while the Angel monitor is on, the Advanced Interrupt Controller (AIC) and the USART channel are enabled.

11. AT915800 Embedded Peripherals I

12. AT Peripherals

13. SYSTEM and USER PERIPHERALS Overview
System Peripherals
External Bus Interface
Advanced Interrupt Controller
Parallel I/O Controller
Watchdog
Peripheral Data Controller
System Timer
Power Management Controller
Real Time Clock
User Peripherals
USART
Serial Peripheral Interface
Timer Counter
Analog to Digital Converter
Digital to Analog Converter
The AT91 microcontrollers integrate several peripherals, which are classified as system or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA bridge and can be programmed with a minimum number of instructions. The peripheral register set is composed of control, mode, data, status and enable/disable/status registers.

14. PIO Controller : Features
Up to 58 Programmable Input Output lines
I/O lines may be multiplexed with an on-chip peripheral signal to optimize the use of available package pins managed by the PIO controller
Input Change Detection Interrupt on each line
Available even in Peripheral mode
Multi Driver (Open-Drain)
Allows multiple devices to drive the PIO lines
Reset state : all PIO configured as PIO in input
PIO Multiplexed with EBI signals do not respect this rule
Depending on the device, the AT91 microcontroller can have up to 2 PIO Controllers. The PIO Controller has 32 programmable IO lines, with pins dedicated as general purpose I/O pins and the other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins.
The PIO Controller enables the generation of an interrupt on input change on any of the PIO pins. After Reset, the pin is controlled by the PIO Controller and is in input.
Each IO can be programmed for multi-driver option. This means that the I/O is configured as open drain in order to support external drivers on the same pin. An external pull-up is necessary to guarantee a logic level of one when the pin is not being driven.

15. PIO Controller : Block Diagram

16. PIO Controller : I/O Levels
Each pin can be configured to be driven high or low
The level is defined in four different ways, according to the following conditions :
If a pin is controlled by the PIO Controller and is not defined as an output, the level is determined by the external circuit.
If a pin is controlled by the PIO Controller and is defined as an output, the level is programmed using the registers Set Output Data (PIO_SODR) and Clear Output Data (PIO_CODR).
If a pin is not controlled by the PIO Controller, the state of the pin is defined by the peripheral.
In all cases, the level on the pin can be read in the register PIO_PDSR (Pin Data Status).

17. AIC : Features 8-level Priority Up to 32 Interrupt sources
Individually maskable
Hardware interrupt vectoring
Internal Interrupt sources
Level sensitive or edge triggered
External Interrupt sources
Low/High level sensitive or positive/negative edge triggered
The AT91 microcontroller embeds an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real time overhead in handling internal and external interrupts. Internal sources are programmed to be level sensitive or edge triggered. External sources can be programmed to be positive or negative edge triggered or high or low level sensitive.

18. AIC : Block Diagram

19. WatchDog : Features 16-bit Down Counter Programmable Time-out Period
4ms to 8s, with 33MHz system clock
4 Clock divide down options
MCK/32, MCK/128, MCK/1024 and MCK/4096
3 Independent Outputs
Internal Reset
Internal Interrupt
Low level on Watchdog overflow signal for a duration of 8 MCK cycles
Control access keys – prevent writes, corruption
The watchdog timer has a 16-bit down counter. Four clock sources are available to the watchdog counter and provides a programmable time-out period of 4ms to 8s with a 33MHz system clock. If an overflow occurs, the watchdog can generate an internal reset, internal interrupt or a low level on the NWDOF signal. All write accesses are protected by control access keys to help prevent corruption of the watchdog.

20. Watchdog : Block Diagram

21. WD : Software Checking
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. In normal operation the user reloads the watchdog at regular intervals before the timer overflow occurs. If an overflow does occur, the watchdog timer generates one or a combination of signals.

22. System Timer : Features
One Period Interval Timer (PIT)
16-bit programmable counter
periodic interrupt, useful for OS, e.g. time slicing
One Watchdog Timer (WD)
maximum watchdog period of 256s with a typical slow clock of kHz
One Real Time Timer (RTT)
20-bit free-running counter
count elapsed seconds
1s increment with a typical slow clock of kHz
count up to s (12 days)
Alarm to generate an interrupt
The System Timer module integrates three different free-running timer: A Period Interval Timer which provides periodic interrupts for use by operating system. It is build around a 16- bit down counter.
A Watchdog timer which can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is buils around a 16-bit down counter. It uses the slow clock divided by 128, this allows the maximum watchdog period to be 256s with a typical slow clock of kHz.
A Real Time Timer, which can be used to count elapsed seconds. It is build around a 20-bit counter. The 20-bit counter can count up to s, corresponding to more than 12 days.

23. ST : Block Diagram

24. Timer Counter : Features
Three 16-bit Timer/Counter channels
Wide range of functions:
Frequency measurement
Event counting
Interval measurement
Pulse generation
Delay timing
Pulse Width Modulation
Clock inputs
3 External and 5 Internal
Two configurable Input/Output signals
Internal interrupt signal
Depending on the device, the AT91 microcontroller can have up to 2 Timer/Counter Blocks. Each containing three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
Each Timer Counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts via the AIC.

25. TC : Block Diagram

26. TC : Clock Selection
Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128, MCK/1024
External clock signals: XC0, XC1, XC2
Selected clock can be inverted
Burst Function
Each channel can independently select an internal or external clock source for its counter: Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128 and MCK/1024, External clock signals: XC0, XC1 and XC2. The selected clock can be inverted to allow counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high.

27. TC : Clock Control
Counter clock can be enabled/disabled and started/stopped
Software Enabling Commands by Control Register : CLKEN and CLKDIS
Loading RB in Capture Mode or RC Compare in Waveform Mode can stop or disable the counter clock
The clock of each counter can be controlled in two different ways, it can be enabled/disabled and started/stopped.

28. TC : Operating Modes
Two different modes:
Capture Mode allows measurement on signals,
Waveform Mode allows wave generation.
Timer Counter Mode programmed with the WAVE bit in the TC Mode Register.
Each Timer Counter channel can independently operate in two different modes: Capture Mode allows measurement on signals Waveform Mode allows wave generation.

29. TC : Triggers
A trigger resets the counter and starts the counter clock.
The following triggers are common to both modes:
Software Trigger
Each channel has a software trigger, available by setting SWTRG in TC_CCR.
SYNC
Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.
Compare RC Trigger
RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR.
External triggers:
TIOA or TIOB in Capture Mode
TIOB, XC0,XCC1 or XC2 in Waveform Mode

30. TC : Capture Mode (1/3) TIOB input TIOA input Capture Register A
Selected
Clock
Capture
Register A
Capture
Register B
Register C
16-bit Counter
RC Compare
SYNC
SWTRG
CPCTRG
LDRA
LDRB
ABETRG
TIOB
input RA
Loading
Logic RB
Loading
Logic
Edge
Detector
Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as input. Registers A and register B are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on signals TIOA and TIOB.
ETRGEDG
TIOA
input
TIOA and TIOB as input pins
RA Loading Logic : can be loaded only after a trigger or if RB has been loaded
RB Loading Logic : can be loaded only after a trigger and if RA has been loaded

31. TC : Capture Mode (2/3) Examples:
Measure the phase between TIOB and TIOA and the duration of the TIOA pulse
TIOB rising edge resets and starts the counter
TIOA rising edge loads RA and a falling edge loads RB
RA contains the phase between TIOB and TIOA
(RB-RA) is the duration of the TIOA pulse

32. TC : Capture Mode (3/3) Measure the duration of a TIOA pulse or period
TIOA falling edge resets and starts the counter and loads RB if RA is already loaded
TIOA rising edge loads RA
RA contains the duration of a TIOA pulse (low level)
RB contains the duration of the TIOA period

33. TC : Waveform Mode (1/2) TIOA output TIOB output TIOB input Register A
Register B
Register C
Selected
Clock
16-bit Counter
RA Compare
RB Compare
RC Compare
ASWTRG
SYNC
AEEVT
TIOA
output
SWTRG
CPCTRG
ACPC
ACPA
ENETRG
EEVT
BSWTRG
XC0
Edge
Detector
BEEVT
TIOB
output
XC1
XC2
BCPC
Waveform Mode allows the TC channel to generate 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or to generate different types of one- shot or repetitive pulses. In this mode, TIOA is configured as ouput and TIOB is defined as ouput if it is not used as an external event. RA, RB and RC are all used as compare registers.
EEVTEDG
BCPB
TIOB
input
TIOA is an output
TIOB can be input or output depending on EEVT programming ( default is input )
Output controllers can set, clear or toggle outputs in function of events

34. TC : Waveform Mode (2/2) Examples:
Dual Pulse Width Modulation (PWM) generation
TIOA is toggled by RA and RC, TIOB by RB and RC
A trigger starts the counter and initializes TIOA and TIOB
The PWM frequency must be stored in the compare register RC
The duty cycles on TIOA and TIOB are defined by RA and RB respectively

35. USART : Features
Programmable Baud Rate Generator with External or Internal Clock
Up to 1Mbits/s in Asynchronous Mode and up to 16Mbits/s in Synchronous Mode at 32MHz
Parity, Framing and Overrun Error Detection
Line Break generation and detection
Automatic Echo, Local Loopback and Loopback Channel Modes
Multi Drop Mode : Address Detection and Generation
Interrupt Generation
2 Dedicated PDC Channels
5,6,7,8 and 9-bit Character Length
Transmitter Time Guard
Depending on the device, the AT91 microcontroller can have up to three identical, full duplex, universal synchronous/asynchronous receiver/transmitters which are connected to the Peripheral Data Controller.

36. USART : Block Diagram

37. USART : Baud Rate Generator
The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the receiver and the transmitter. The Baud Rate Generator can select between external and internal clock sources. The external clock source is SCK and the internal clock sources can be either the master clock MCK or the master clock divided by 8 (MCK/8).
Asynchronous Mode
Baud rate = MCK period / 16 / CD
Synchronous Mode
Baud Rate = MCK period / CD

38. Asynchronous: 8 bit 1 start and 1 stop
USART : Reception
Asynchronous: 8 bit 1 start and 1 stop
Synchronous: 8 bit 1 start and 1 stop
In Asynchronous mode, the USART detects the start of a received character by sampling the RXD signal until it detects a valid start bit. when a valid start bit has been detected, the receiver samples the RXD at the theorical mid-point of each bit. In Synchronous Mode, the receiver samples the RXD signal on each rising edge of the baud rate clock.

39. Asynchronous and Synchronous : 8 bit, parity and 1 stop
USART : Transmission
Asynchronous and Synchronous : 8 bit, parity and 1 stop
The transmitter has the same behavior in both synchronous and asynchronous operating modes. Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first, on the falling edge of the serial clock.

40. USART : PDC Channels PDC shares the ASB bus with the ARM Core
External or Internal Memories Access
ARM Core stopped during 3 cycles min.
Each PDC channel is dedicated to a peripheral and a transfer direction
PDC Registers mapped in User Interface
End of Transfer in the Status Register
Typical Application
Code download
Packet Exchange
Receiver Timeout Helps to Support Variable Length Packets
Transmitter Time Guard helps to Support Slow Remote Devices
PDC Channel
ARM Core
ASB Arbiter
USART
RXRDY
PDC Receive Channel
RXEND
Size = Byte
TXRDY
PDC Transmit Channel
The PDC channels allow to transfert data from on-chip peripherals such as USART, SPI to on- chip memories without CPU intervention.Each USART channel is closely connected to a corresponding Peripheral Dedicated Controller channel. One is dedicated to the receiver, the other is dedicated to the transmitter.
TXEND
Size = Byte

41. SPI : Features Serial Interface between CPU and External Peripherals
Master or Slave Mode
Full duplex 3 wires synchronous transfer
MISO: Master In Slave Out
MOSI: Master Out Slave In
SPCK: SPI Clock
Maximum SPI baud rate clock: MCK/4
4 External Slave chip selects
8 to 16-bit Programmable Data Length
Mode Fault Detection in Master Mode
2 Dedicated PDC Channels
Depending on the device, the AT91 microcontroller can have up to 2 SPIs which provide communication with external devices in master or slave mode. The SPI has four external chip selects which can be connected to up to 15 devices. The data length is programmable, from 8 to 16-bit. As for the USART, a 2-channel PDC can be used to move data between memory and the SPI without CPU intervention.

42. SPI Timing (example)

43. SPI : Block Diagram

44. SPI : Bus Implementations
Up to 4 Peripherals
Up to 15 Peripherals with Decoding
AT91
AT91
SPI
SPI
4 to 16
Decoder
NPCS3
Q14
Serial
Peripheral
NPCS2
Serial
Peripheral
Q13
Serial
Peripheral
NPCS1
Serial
Peripheral
Q12
Serial
Peripheral
NPCS0
Serial
Peripheral
Q11
Serial
Peripheral
Serial
Peripheral
Q10
Serial
Peripheral Q1
Serial
Peripheral Q0
Serial
Peripheral
4 different protocols possible
First Bit set in NPCS field
4 different protocols possible
0-3, 4-7, 8-11, 12-14
Peripheral 15 is reserved for no selection

45. RTC : Real Time Clock (1/2)
Available on the AT91M55800A only
Features
Low power consumption
Complete time of day clock
Programmable periodic interrupts
Alarm
Five programmable fields: Month, Date, Sec, Min and Hour
Y2K compliant
BCD Format
The AT91M55800A features a Real Time Clock (RTC) peripheral that is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two hundred year calendar, complemented by a programmable periodic interrupt. The time and calendar value are coded in Binary Coded Decimal (BCD) format.

46. RTC : Real Time Clock (2/2)
Block Diagram

47. ADC : Analog to Digital Converter (1/2)
Available on the AT91M55800A
Features
Two identical 4-channel ADC
10-bit resolution
Successive Approximation Register (SAR) approach
Settable analog input conversion range (dedicated VREF)
11 ADC clock cycles conversion time including 1 ADC clock cycle for sample and hold (e.g. 10µs for one channel at maximum clock rate)
4 LSB Maximum Integral Non-linearity
Sleep mode (energy saving)
Starting modes:
Software trigger
External input (A/D trigger)
Timers on-chip event signal
Dedicated analog power supply pins (VDDA and GNDA)
Improve noise rejection
End of conversion interrupt
The AT91M55800A features two identical 4-channel 10-bit Analog-to-digital converters (ADC) based on a Successive Approximation Register (SAR) approach.

48. ADC : Analog to Digital Converter (2/2)
Block Diagram
Each ADC has 4 analog input pins (AD0 to AD3 and AD4 to AD7), digital trigger input pins (AD0TRIG and AD1TRIG), and provides an interrupt signal to the AIC. Both ADCs share the analog power supply pins (VDDA and GNDA) and the input reference voltage pin (ADVREF).

49. DAC : Digital to Analog Converter (1/2)
Available on the AT91M55800A
Features
Two identical 1-channel DAC
10-bit resolution
6µs maximum settling time
Settable analog output range (dedicated VREF)
4 LSB Maximum Integral Non-linearity
Starting modes:
software trigger
Timers on-chip event signal
Dedicated analog power supply pins (VDDA and GNDA)
Improve noise rejection
Data ready interrupt
The AT91M55800A features two identical 1-channel 10-bit Digital to Analoc Converters (DAC).

50. DAC : Digital to Analog Converter (2/2)
Block Diagram
Each DAC has an analog output pin (DA0 and DA1) and provides an interrupt signal to the AIC (DA0IRQ and DA1IRQ).

51. PIO The Parallel I/O Controller

52. The I/O Pins
The PIO lines are controller by two separate and identical PIO controllers called PIOA and PIOB
PIO
PIOA
Fast Interrupt
External Interrupt 0 - 3
x25 Peripheral Pins
Boot Mode Select (BMS)
x13 General Purpose I/O Lines
External Interrupts 4 - 5
x12 Peripheral Pins
PIOB

53. PIO Control (x12) & Status (8) Registers
Peripheral Enable
Peripheral Disable
Output Enable
Output Disable
Enable Glitch Filter
Disable Glitch Filter
Set Bit
Clear Bit

54. PIO Enable Register
For PIOB

55. Parallel I/O Multiplexed with a Bi-directional Signal

56. EBI The External Bus Interface

57. The I/O Pins
The EBI generates the signals that control the access to the external memory or peripheral devices. The EBI is fully-programmable and can address up to 128M bytes.
EBI
A0 – A23 (A0 / NLB)
D0 – D15
NSC0 – NSC7
NRD / NOE
NWR0 / NWE
MNWR1 / NUB
NWAIT

58. Data Bus Width
8-bit Data Bus 16-bit Data Bus

59. 2 x 8 – bit Data Bus

60. Read Protocol
Standard Early

61. Standard Wait States

62. EBI User Interface

63. EBI Chip Select Register
EBI_CSR0 – EBI_CSR7 ( 0xFFE00000 – 0xFFE0001C )

64. Wait States

65. Pages & TDF

66. AIC Advanced Interrupt Controller

67. What are interrupts ? Stops the execution of main software
Redirects the program flow, based on an event, to execute a different software subroutine
Interrupt behaviour :
Main loop :
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Interrupt routine :
Instruction A
Instruction B
Instruction C
Return from interrupt
During the normal flow of program execution, it is common for an event to occur requiring the microcontroller to stop what it’s doing and perform another task, such as read an A/D register, program a timer, or respond to an external event. The event that can cause program execution to stop and direct the core's attention to another task is called an interrupt.
The microcontroller then redirects program flow to an Interrupt Service Routine, which is a piece of software written to respond to the specific interrupt event.
A microcontroller may be executing the main loop of software, running tasks. When an interrupt occurs, program execution stops and the present state of the microcontroller, including the instruction being executed, are saved. When the interrupt service routine is finished, the program retrieves the state of the microcontroller that was stored before and resumes program execution at where it left off.

68. Interrupt sources (1) External Interrupts
Allows an external event to stop program execution
Can alert the core by an edge transition or a level
Signal can originate from external peripherals or systems
Example: external switch closure Interrupts
AT91
External interrupts can occur from any source. Pins on the microcontroller, called interrupt pins, can alert the microcontroller of an event by a transition on the pin. On Atmel AT91 microcontrollers, an interrupt can be initiated by a high or low level on the interrupt pin, or by the pin changing from high to low, or from low to high. The interrupt signal can originate from an external peripheral or system.

69. Interrupt sources (2) Internal Interrupts
Originate from on-chip peripherals
Notifies core that peripheral needs servicing
Typically can occur at any time
Can originate from software
Timer/Counter
ADC
USART
End of conversion
Counter overflow
End of transmission
Internal interrupts usually originate from one of the on-chip peripherals. Some examples are shown here. An A/D converter can interrupt the core when it is finished converting, so that the software may read and act on the data. A timer may generate an interrupt after it has completed measuring a period of time. There is also a special class of internal interrupt called a software interrupt.

70. ARM7TDMI Interrupt Sources
Two physically independent sources
Fast interrupt : FIQ
Used for fast interrupt handling
Private registers
Enable/disable with F bit in CPSR
Last vector in the exception vector table
Interrupt : IRQ
Standard interrupt request
Enable/disable with I bit in CPSR
ARM7TDMI Processor
IRQ
FIQ
The ARM7TDMI processor implements two physically independent sources of interrupt: The FIQ (Fast Interrupt Request) is designed to support a data transfer and has sufficient private registers to remove the need for register saving (thus minimising the overhead of context switching). FIQ may be disabled by setting the CPSR’s F flag.
The IRQ (Interrupt Request) is a normal interrupt. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting the I bit in the CPSR.

71. Advanced Interrupt Controller (1)
Features
8-level Priority
Up to 32 Interrupt sources
Individually maskable
Hardware interrupt vectoring
Internal Interrupt sources
Level sensitive or edge triggered
External Interrupt sources
Low/High level sensitive or positive/negative edge triggered
The AT91 microcontroller features the Advanced Interrupt Controller (AIC), an 8-level priority, individually maskable, vectored interrupt controller. Internal sources are programmed to be level sensitive or edge triggered. External sources can be programmed to be positive or negative edge triggered or high or low level sensitive.

72. Advanced Interrupt Controller (2)
Block Diagram
The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor's NFIQ line can only be asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt sources.

73. Advanced Interrupt Controller (3)
The Advanced Interrupt Controller (AIC) can have up to 32 interrupt sources. The interrupt sources are listed in this table.

74. AIC User Interface
AT91m55800 Manual page 101

75. Interrupt Vectors
Each interrupt source is associated with a Source Vector Register (AIC_SVR0 - AIC_SVR31) which contains the address of the interrupt handler
When the Interrupt Vector Register (AIC_IVR) is read, it automatically returns the contents of the source vector register corresponding to the active interrupt
SWI
ABORT (Fetch)
UNDEF
RESET
FIQ
IRQ
ABORT (Data)
0xFFFFF100
0xFFFFF104
0x C 0x
0xFFFFF080
0xFFFFF0FC
AIC_FVR
AIC_IVR
AIC Source vectors
AIC_SVR31
AIC Interrupt vectors
ARM Exception vectors
ldr pc,[pc,#-&F20]
Index =
Interrupt Id.
AIC_SVR30
AIC_SVR0
AIC_SVR1
AIC_ISR
The hardware interrupt vectoring reduces the number of instructions to reach the interrupt handler to only one. This feature consists of a set of registers which provide the address of the handler to execute according to the source of an interrupt.
Each interrupt source is associated with a Source Vector Register (AIC_SVR0-AIC_SVR31) which contains the address of the function corresponding to the active interrupt. In order to take advantages of the hardware interrupt vectoring it is necessary to store the address of each interrupt handler in the corresponding AIC_SVR, at system initialization.
When the Interrupt Vector Register (AIC_IVR) is read, it automatically returns the contents of the source vector register corresponding to the active interrupt with the highest priority. Each interrupt source has its corresponding AIC_SVR.

76. Interrupt Prioritization (1)
The NIRQ line is controlled by an 8-level priority encoder
Each source has a programmable priority level of 7 to 0. Level 7 is the highest priority.
The AIC manages the prioritization by using an internal stack on which the current interrupt level is automatically pushed when AIC_IVR is read, and popped when AIC_EOICR (end of interrupt command reg.) is written
Between these two events, the software can manage the state and the mode of the core in order to re-enable the IRQ line and to allow an interrupt with a higher priority.

77. Interrupt Prioritization (2)
When an interrupt is managed by the processor, R14_irq and SPSR_irq are automatically overwritten without being saved
It is mandatory to save these registers before re-enabling the IRQ line and to restore them before exiting the interrupt routine
If the interrupt treatment performs function calls (Branch with link), R14_irq is used. In this case, IRQ can not be re-enabled while the processor is in IRQ mode
It is mandatory to first change the processor mode to SYSTEM mode in order to keep all exceptions available

78. Interrupt Prioritization (3)
The standard sequence of an interrupt handler is:
Validate the nested interrupts
Save R14_irq and SPSR_irq in the IRQ stack
Set the mode bits in CPSR with the SYSTEM Mode value
Re-enable IRQ by clearing bit I in CPSR
Perfom interrupt treatment
call C handler
Disable the nested interrupts
Disable IRQ by clearing bit I in CPSR
Set the mode bits in CPSR with the IRQ Mode value
Restore R14_irq and SPSR_irq from the IRQ stack
This sequence is automatically preceded by a read of AIC_IVR and must be followed by a write in AIC_EOICR before exiting from the interrupt

79. Interrupt Prioritization (4/4)

80. Spurious Interrupt (1)
A Spurious Interrupt occurs when the ARM7TDMI processor is interrupted and the source of interrupt has disappeared when IVR is read :
With any sources programmed to be level sensitive, if the interrupt signal of the AIC input is de-asserted at the same time as it is taken into account by the ARM7TDMI.
If an interrupt is asserted at the same time as the software is disabling the corresponding source through AIC_IDCR.

81. Spurious Interrupt (2)
The AIC is able to detect these Spurious Interrupts and returns the Spurious Vector when the IVR is read
The Spurious Vector can be programmed by the user when the vector table is initialized.
It is mandatory for the Spurious Interrupt Service Routine to acknowledge the “Spurious” behavior by writing to the AIC_EOICR (End of Interrupt) before returning to the interrupted software.
Spurious Interrupt Service Routine Sequence:
Adjust and save lr_irq in stack
Write the End of Interrupt Command Register
Run a trace function if necessary
Returns by restoring LR directly in PC