Introduction to Microcontrollers

Introduction to Microcontrollers
Lecture 1: Introduction, Embedded Systems, Product Life-Cycle, ARM Programming Bard, Gerstlauer, Valvano, Yerraballi

Agenda Course Description Embedded Systems Product Life Cycle
Book, Labs, Equipment Grading Criteria Expectations/Responsibilities Prerequisites Embedded Systems Microcontrollers Product Life Cycle Analysis, Design, Implementation, Testing Flowcharts, Data-Flow and Call Graphs ARM Architecture Programming Integrated Development Environment (IDE) To do this week: get book, order a board, {read chapters 1 and 2 of the book or ebook 2 3 4}, do ws01, do HW0, install Keil uVision 4.73 on laptop Bard, Gerstlauer, Valvano, Yerraballi

EE306 Recap: Digital Logic
AND, OR, NOT Flip flops Registers Positive logic: Negative logic : True is higher voltage True is lower voltage False is lower voltage False is higher voltage Bard, Gerstlauer, Valvano, Yerraballi

EE302 Recap: Ohm’s Law V = I * R Voltage = Current * Resistance
I = V / R Current = Voltage / Resistance R = V / I Resistance = Voltage / Current P = V * I Power = Voltage * Current P = V2 / R Power = Voltage2 / Resistance P = I2 * R Power = Current2 * Resistance Bard, Gerstlauer, Valvano, Yerraballi

Embedded System Embedded Systems are everywhere MicroProcessor
Ubiquitous, invisible Hidden (computer inside) Dedicated purpose MicroProcessor Intel: 4004, ,.. x86 Motorola: 6800, ,.. PowerPC ARM, DEC, SPARC, MIPS, PowerPC, Natl. Semi.,… MicroController Processor+Memory+ I/O Ports (Interfaces) Consumer electronics: Washing machine, Exercise equipment, Remote controls, Clocks and watches, Games and toys, Audio/video electronics, Set- back thermostats, Camera, Camcoder, Television, VCR, cable box Communication systems: Answering machines, Telephones, Fax machines, Radios, Cellular phones, pagers Automotive systems: Automatic breaking, Noise cancellation, Locks, Electronic ignition, Power windows and seats, Cruise control, Collision avoidance, Climate control, Emission control, Instrumentation Military hardware: Smart weapons, Missile guidance systems, Global positioning systems, Surveillance systems Business applications: Cash registers, Vending machines, ATM machines, Traffic controllers, Industrial robots, Bar code readers and writers, Automatic sprinklers, Elevator controllers, RFID systems, Lighting and heating systems Medical devices: Monitors, Drug delivery systems, Cancer treatments, Pacemakers, Prosthetic devices, Dialysis machines Bard, Gerstlauer, Valvano, Yerraballi

Embedded Systems A reactive system continuously A real time system
accepts inputs performs calculations generates outputs A real time system Specifies an upper bound on the time required to perform the input/calculation/output in reaction to external events Bard, Gerstlauer, Valvano, Yerraballi

Microcontroller I/O Processor – Instruction Set CISC vs. RISC Memory
Non-Volatile ROM EPROM, EEPROM, Flash Volatile RAM (DRAM, SRAM) Interfaces H/W: Ports S/W: Device Driver Parallel, Serial, Analog, Time I/O Memory-mapped vs. I/O mapped Processor There are two classifications of computers: complex instruction set computer (CISC) and reduced instruction set computer (RISC). In reality, there is a spectrum of architectures that we can classify as CISC or RISC. We make these general observations when deciding whether to call a computer CISC or RISC: Complex instruction set computers (CISC) Early computers offered CPUs that were much faster than available memories. Fetching instructions limited performance A single complex instruction could perform many operations Example: Find the zeros of a polynomial Complex instructions require many processor clock cycles to complete and most instructions can access memory A program running on a CISC computer employed a relatively small number of complex instructions High code density, many instruction types w/ varying length, fewer and specialized registers, many addressing modes Complexity is embedded in the processor hardware (overhead) Examples: Intel (x86), Freescal 9S12 Reduced Instruction Set Computers (RISC) Memories match CPU speed No large penalty for instruction fetch Instructions simplified Example: dedicated load/store instructions, regular instructions can not access memory but only registers Single processor clock cycle per instruction (pipelined) A program running on a RISC computer employs a relatively larger number of simplified instructions Reduced code density, few instructions w/ fixed delay (pipeline!), many identical general-purpose registers, few addressing modes Complexity exists in the assembly code generated by the programmer or compiler, hardware is simple (low overhead/low power) Examples: LC3, MIPS, ARM, SPARC, PowerPC Which architecture is best is beyond the scope of this class, but it is important to recognize the terminology. It is very difficult to compare the execution speed of two computers, especially between a CISC and a RISC. One way to compare is to run a benchmark program on both, and measure the time it takes to execute. Time to execute benchmark = Instructions/program * Average cycles/instruction * Seconds/cycle For example, the 50 MHz ARM Cortex M has one bus cycle every 20ns. One average it may require 1.5 cycles per instruction. If the benchmark program executes 10,000,000 assembly instructions, then the time to execute the benchmark will be 0.3 seconds. Memory: EPROMs are Erasable Programmable ROMs. The mechanism used to erase and write is UV light EEPROMs are Electrically Erasable Flash memory is like EEPROM however writes are performed in large blocks as opposed to single bytes. Cheaper hence popular DRAMs require a periodic refresh SRAMs don’t. Both are volatile therefore are lost when powered down. Interfaces: Parallel - binary data is available simultaneously on groups of lines Serial - binary data is available one bit at a time on a single line Analog - data is encoded as a variable voltage Time - data is encoded as a period, frequency, pulse width or phase shift I/O Memory-mapped I/O I/O ports/registers appear as addresses on common bus with memory I/O ports/registers are accessed as though they are locations in memory Employed on the ARM, Freescale and TI processors I/O-mapped I/O I/O ports/registers have separate control signals from those used with memory Special instructions are used to access I/O ports/registers Employed on Intel x86 processors Bard, Gerstlauer, Valvano, Yerraballi

Texas Instruments TM4C123 ARM Cortex-M4 + 256K EEPROM + 32K RAM + JTAG
+ Ports + SysTick + ADC + UART Bard, Gerstlauer, Valvano, Yerraballi

Product Life Cycle Analysis (What?) Implementation(Real)
Requirements -> Specifications Design (How?) High-Level: Block Diagrams Engineering: Algorithms, Data Structures, Interfacing Implementation(Real) Hardware, Software Testing (Works?) Validation:Correctness Performance: Efficiency Maintenance (Improve) Requirements are broad and Specifications go into the details. Bard, Gerstlauer, Valvano, Yerraballi

Lab 8: Position Measurement System
Data Flow Graph Lab 8: Position Measurement System A data flow-graph showing how the position signal passes through the system Rectangles represent h/w components and Ovals represent s/w modules Data flow-graphs give a high-level design of the system showing the flow of “information” Bard, Gerstlauer, Valvano, Yerraballi

Position Measurement System
Call Flow Graph Position Measurement System Call Flow-Graphs give a high-level details of the various modules (hardware and software) and their interactions. Normally h/w is passive and software initiates communication between the h/w and s/w. However it is possible for the h/w to initiate communication by using interrupts. The h/w causes an interrupt in response to which an ISR (interrupt service routine) is executed. The Timer ISR in this system gets the next sample from the ADC driver, converts it to a position value and sends it to the LCD driver for display on the LCD h/w. Bard, Gerstlauer, Valvano, Yerraballi

Structured Programming
Common Constructs (as Flowcharts) The Fork-Join construct is used in Parallel programming. This is different from multi-threading used in concurrent (Distributed) programming. In multi- threading there may be multiple threads that are active but at any given instant only one of them is being executed. In desktop systems that have multiple cores and parallel computers with several processors, multiple threads can be simultaneously executed. Bard, Gerstlauer, Valvano, Yerraballi

Flowchart Toaster oven:
Coding in assembly and/or high-level language (C) Bard, Gerstlauer, Valvano, Yerraballi

Flowchart Example 1.3. Design a flowchart for a system that performs two independent tasks. The first task is to output a 20 kHz square wave on PORTA in real time (period is 50 ms). The second task is to read a value from PORTB, divide the value by 4, add 12, and output the result on PORTD. This second task is repeated over and over. < : Hardware Interrupt causing the main program to be suspended and the corresponding ISR to execute > : Return from Interrupt causing the control to be returned to the point where the main program was suspended. The execution sequence of this simple system might be something like: ABCDB<E>CDBC<E>DBCD<E>BCD… We say this code is multi-threaded because we have two threads: The foreground thread computes the primes and the background thread issues a pulse. They are both active at the same time. Bard, Gerstlauer, Valvano, Yerraballi 14

ARM Cortex M4-based System
ARM Cortex-M4 processor Harvard architecture Different busses for instructions and data RISC machine Pipelining effectively provides single cycle operation for many instructions Thumb-2 configuration employs both 16 and 32 bit instructions The LC3 computer from EE 306 had an address space of 64Ki and an addressability of 16-bit for a total of 128KiB. The Memory Address Register (MAR) is 16 bits and the Memory Data Register (MDR) is also 16-bits. Vs. On the ARM, the MAR is still 32-bits. Total addressable memory is 4GiB. It has flexible addressability (bit,byte-8bits,halfword-16bits,word-32bits) Bard, Gerstlauer, Valvano, Yerraballi

ARM ISA: Thumb2 Instruction Set
Variable-length instructions ARM instructions are a fixed length of 32 bits Thumb instructions are a fixed length of 16 bits Thumb-2 instructions can be either 16-bit or 32-bit Thumb-2 gives approximately 26% improvement in code density over ARM Thumb-2 gives approximately 25% improvement in performance over Thumb Bard, Gerstlauer, Valvano, Yerraballi

ARM ISA: Registers, Memory-map
The PC points to the address of the current instruction (Program Counter) The Link Register is akin to Register R7 in LC3 used to store the return address on subroutine calls. The stack is a temporary storage implemented in the RAM. We push and pop elements onto and off the stack as we desire. The stack pointer (SP) keeps track of the current location of the “top” of the stack. The CC (condition-code) bits contains codes that reflect the results of the most recent instruction. Many “branch” type instructions “test” these bits for their operation. The Program Status Register (PSR) has them. Condition Code Bit s Indicates N negative Result is negative Z zero Result is zero V overflow Signed overflow C carry Unsigned overflow TI TM4C123 Microcontroller Bard, Gerstlauer, Valvano, Yerraballi

LC3 to ARM - Data Movement
LEA R0, Label ;R0 <- PC + Offset to Label ADR R0,Label or LDR R0,=Label LD R1,Label ; R1 <- M[PC + Offset] LDR R0,=Label ; Two steps: (i) Get address into R0 LDRH R1,[R0] ; (ii) Get content of address [R0] into R1 LDR R1,R0,n ; R1 <- M[R0+n] LDRH R1,[R0,#n] LDI R1,Label ; R1 <- M[M[PC + Offset]] ; Three steps!! ST R1,Label ; R1 -> M[PC + Offset] LDR R0,=Label ; Two steps: (i)Get address into R0 STRH R1,[R0] ; (ii) Put R1 contents into address in R0 STR R1,R0,n ; R1 -> M[R0+n] STRH R1,[R0,#n] STI R1,Label ; R1 -> M[M[PC + Offset]] Bard, Gerstlauer, Valvano, Yerraballi

LC3 to ARM – Arithmetic/Logic
ADD R1, R2, R3 ; R1 <- R2 + R3 ADD R1,R2,R3 ; 32-bit only ADD R1,R2,#5 ; R1 <- R2 + 5 ADD R1,R2,#5 ; 32-bit only, Immediate is 12-bit AND R1,R2,R3 ; R1 <- R2 & R3 AND R1, R2, R3 ; 32-bit only AND R1,R2,#1 ; R1 <- Bit 0 of R2 AND R1, R2, #1 ; 32-bit only NOT R1,R2 ; R1 -> ~(R2) EOR R1,R2,#-1 ; -1 is 0xFFFFFFFF, ; so bit XOR with 1 gives complement Bard, Gerstlauer, Valvano, Yerraballi

LC3 to ARM – Branches BR Target ; PC <- Address of Target B Target BRnzp Target ; PC <- Address of Target BRn Target ; PC <- Address of Target if N=1 BMI Target ; Branch on Minus BRz Target ; PC <- Address of Target if Z=1 BEQ Target BRp Target ; PC <- Address of Target if P=1 No Equivalent BRnp Target ; PC <- Address of Target if Z=0 BNE Target BRzp Target ; PC <- Address of Target if N=0 BPL Target ; Branch on positive or zero (Plus) BRnz Target ; PC <- Address of Target if P=0 Bard, Gerstlauer, Valvano, Yerraballi

LC3 to ARM – Subs,TRAP,Interrupt
JSR Sub ; PC <- Address of Sub, Return address in R7 BL Sub ; PC<-Address of Sub, Ret. Addr in R14 (Link Reg) JSRR R4 ; PC <- R4, Return address in R7 BLX R4 ; PC <-R4, Return address in R14 (Link Reg) RET ; PC <- R7 (Implicit JMP to address in R7) BX LR ; PC <- R14 (Link Reg) JMP R2 ; PC <- R2 BX R2 ; PC <- R14 (Link Reg) TRAP x25 ; PC <- M[x0025], Return address in R7 SVC #0x25 ; Similar in concept but not implementation RTI ; Pop PC and PSR from Supervisor Stack… BX LR ; PC <- R14 (Link Reg) [same as RET] Bard, Gerstlauer, Valvano, Yerraballi

SW Development Environment
Bard, Gerstlauer, Valvano, Yerraballi

EE 319K Introduction to Embedded Systems
Lecture 2: I/O, Logic/Shift Operations, Addressing modes, Memory Operations, Subroutines, Introduction to C Bard, Gerstlauer, Valvano, Yerraballi

Agenda Recap Outline Embedded systems Product life cycle
ARM programming Outline Input/output Logical/shift operations Addressing modes, memory operations Stack and subroutines Introduction to C Structure of a C program Variables, expressions and assignments Bard, Gerstlauer, Valvano, Yerraballi

Input/Output: TM4C123 6 General-Purpose I/O (GPIO) ports:
Four 8-bit ports (A, B, C, D) One 6-bit port (E) One 5-bit port (F) Bard, Gerstlauer, Valvano, Yerraballi

I/O Ports and Control Registers
GPIO_PORTF_DATA_R GPIO_PORTF_DIR_R The input/output direction of a bidirectional port is specified by its direction register. GPIO_PORTF_DIR_R , specify if corresponding pin is input or output: 0 means input 1 means output Bard, Gerstlauer, Valvano, Yerraballi

I/O Ports and Control Registers
Address 7 6 5 4 3 2 1 Name 400F.E108 - GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_RCGC2_R FC DATA GPIO_PORTF_DATA_R DIR GPIO_PORTF_DIR_R SEL GPIO_PORTF_AFSEL_R C DEN GPIO_PORTF_DEN_R Initialization (executed once at beginning) Turn on clock in SYSCTL_RCGC2_R Wait two bus cycles (two NOP instructions) Set DIR to 1 for output or 0 for input Clear AFSEL bits to 0 to select regular I/O Set DEN bits to 1 to enable data pins Input/output from pin Read/write GPIO_PORTF_DATA_R Bard, Gerstlauer, Valvano, Yerraballi

Logic Operations Logic Instructions A Rn B Operand2 A&B AND A|B ORR
EOR A&(~B) BIC A|(~B) ORN 1 Logic Instructions AND{S} {Rd,} Rn, <op2> ; Rd=Rn&op2 ORR{S} {Rd,} Rn, <op2> ; Rd=Rn|op2 EOR{S} {Rd,} Rn, <op2> ; Rd=Rn^op2 BIC{S} {Rd,} Rn, <op2> ; Rd=Rn&(~op2) ORN{S} {Rd,} Rn, <op2> ; Rd=Rn|(~op2) Bard, Gerstlauer, Valvano, Yerraballi

To set The or operation to set bits 1 and 0 of a register.
The other six bits remain constant. Friendly software modifies just the bits that need to be. GPIO_PORTD_DIR_R |= 0x03; // PD1,PD0 outputs Assembly: LDR R0,=GPIO_PORTD_DIR_R LDR R1,[R0] ; read previous value ORR R1,R1,#0x03 ; set bits 0 and 1 STR R1,[R0] ; update c7 c6 c5 c4 c3 c2 c1 c0 value of R1 x03 constant c7 c6 c5 c4 c3 c result of the ORR Bard, Gerstlauer, Valvano, Yerraballi

To toggle The exclusive or operation can also be used to toggle bits.
GPIO_PORTD_DATA_R ^= 0x80; /* toggle PD7 */ Assembly: LDR R0,=GPIO_PORTD_DATA_R LDR R1,[R0] ; read port D EOR R1,R1,#0x80 ; toggle bit 7 STR R1,[R0] ; update b7 b6 b5 b4 b3 b2 b1 b0 value of R1 x80 constant ~b7 b6 b5 b4 b3 b2 b1 b0 result of the EOR Bard, Gerstlauer, Valvano, Yerraballi

Switch Interfacing The and operation to extract, or mask, individual bits: Pressed = GPIO_PORTA_DATA_R & 0x10; //true if the PA6 switch pressed Assembly: LDR R0,=GPIO_PORTA_DATA_R LDR R1,[R0] ; read port A AND R1,R1,#0x10 ; clear all bits except bit 6 LDR R0,=Pressed ; update variable STR R1,[R0] ; true iff switch pressed a7 a6 a5 a4 a3 a2 a1 a0 value of R1 x40 constant 0 a result of the AND Bard, Gerstlauer, Valvano, Yerraballi

Shift Operations Use the ASR instruction when manipulating signed numbers, and use the LSR instruction when shifting unsigned numbers Bard, Gerstlauer, Valvano, Yerraballi

Shift Example Assembly:
High and Low are unsigned 4-bit components, which will be combined into a single unsigned 8-bit Result. Result = (High<<4)|Low; Assembly: LDR R0,=High LDR R1,[R0] ; read value of High LSL R1,R1,#4 ; shift into position LDR R0,=Low LDR R2,[R0] ; read value of Low ORR R1,R1,R2 ; combine the two parts LDR R0,=Result STR R1,[R0] ; save the answer h3 h2 h1 h0 value of High in R1 h3 h2 h1 h after last LSL l3 l2 l1 l0 value of Low in R2 h3 h2 h1 h0 l3 l2 l1 l0 result of the ORR instruction Bard, Gerstlauer, Valvano, Yerraballi

Design example Market survey, profit estimate
Overall function, specifications Data flow (test) Flowchart (test) Software (test) Simulation, prototype (test) Build (test) Bard, Gerstlauer, Valvano, Yerraballi

Design Function table (PD0 input, PD3 output)
How to test (switch input, LED output) Draw a data flow graph Draw a flow chart Write pseudo code Write assembly Simulate Bard, Gerstlauer, Valvano, Yerraballi

Process Open GPIO_4F120asm project, edit, simulate
Start Activate clock for port Enable PD3, PD0 pins Make PD0 (switch) pin an input Make PD3 (LED) pin an output Loop Read input from Switch (0 or 1) not function LED = 8*(not Switch) Write output (8 or 0) branch Loop Build it, run it, test it with logic analyzer Bard, Gerstlauer, Valvano, Yerraballi

ARM Assembly Language Assembly format Comments
Label Opcode Operands Comment init MOV R0, #100 ; set table size BX LR Comments Comments should explain why or how Comments should not explain the opcode and its operands Comments are a major component of self-documenting code What does BX LR do? Bard, Gerstlauer, Valvano, Yerraballi

Simple Addressing Modes
Second operand - <op2> ADD Rd, Rn, <op2> Constant ADD Rd, Rn, #constant ; Rd = Rn+constant Shift ADD R0, R1, LSL # ; R0 = R0+(R1*16) ADD R0, R1, R2, ASR #4 ; R0 = R1+(R2/16) Memory accessed only with LDR STR Constant in ROM: =Constant / [PC,#offs] Variable on the stack: [SP,#offs] Global variable in RAM: [Rx] I/O port: [Rx] Bard, Gerstlauer, Valvano, Yerraballi

Addressing Modes Immediate addressing
Data is contained in the instruction MOV R0,# ; R0=100, immediate addressing List two ways to bring a constant into a register? Bard, Gerstlauer, Valvano, Yerraballi

Addressing Modes Indexed Addressing
Address of the data in memory is in a register LDR R0,[R1] ; R0= value pointed to by R1 Is the number 0x in general? In this example Bard, Gerstlauer, Valvano, Yerraballi

Addressing Modes PC Relative Addressing
Address of data in EEPROM is indexed based upon the Program Counter The Cortex-M3 has a 32-bit address space Instructions are at most 32 bits long => there is not enough space in an instruction for an address EEPROM accesses can be indexed using the program counter The PC always points to EEPROM and it can be used to calculate an address relative to the value in the PC RAM accesses involve storing the address in EEPROM and then accessing it using indexed addressing relative to the PC Two instructions will typically be required to access RAM or I/O Bard, Gerstlauer, Valvano, Yerraballi

Memory Access Instructions
Loading a register with a constant, address, or data LDR Rd, =number LDR Rd, =label LDR and STR used to load/store RAM using register-indexed addressing Register [R0] Base address plus offset [R0,#16] ADR Rd,val is a pseudo-op that gets assembled into ADD Rd,PC,#offs Can only load values that are addresses (relative to PC) Offset is 8 bit, i.e. address must be within 255 bytes of PC LDR Rd,=val is a pseudo-op that gets assembled into either a MOV Rd,#val or a constant in ROM with LDR Rd,[pc,#offs] Can be any constant (number/value) or address Bard, Gerstlauer, Valvano, Yerraballi

Load/Store Instructions
General load/store instruction format LDR{type} Rd,[Rn] ;load memory at [Rn] to Rd STR{type} Rt,[Rn] ;store Rt to memory at [Rn] LDR{type} Rd,[Rn, #n] ;load memory at [Rn+n] to Rd STR{type} Rt,[Rn, #n] ;store Rt to memory [Rn+n] LDR{type} Rd,[Rn,Rm,LSL #n] ;load [Rn+Rm<<n] to Rd STR{type} Rt,[Rn,Rm,LSL #n] ;store Rt to [Rn+Rm<<n] Aligned/Unaligned Memory Access Aligned word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access Unaligned accessing a 32-bit object (4 bytes) but the address is not evenly divisible by 4 accessing a 16-bit object (2 bytes) but the address is not evenly divisible by 2 Unaligned access supported for the following instructions: LDR Load 32-bit word LDRH Load 16-bit unsigned halfword LDRSH Load 16-bit signed halfword (sign extend bit 15 to bits 31-16) STR Store 32-bit word STRH Store 16-bit halfword Bard, Gerstlauer, Valvano, Yerraballi

The Stack Stack is last-in-first-out (LIFO) storage
32-bit data Stack pointer, SP or R13, points to top element of stack Stack pointer decremented as data placed on stack PUSH and POP instructions used to load and retrieve data Bard, Gerstlauer, Valvano, Yerraballi

The Stack Stack is last-in-first-out (LIFO) storage
32-bit data Stack pointer, SP or R13, points to top element of stack Stack pointer decremented as data placed on stack (incremented when data is removed) PUSH and POP instructions used to load and retrieve data Stack push first decrements SP, then stores the data Stack pop first reads the data, and then increments SP Instruction sequence: PUSH {R0} PUSH {R1} PUSH {R2} POP {R3} POP {R4} POP {R5} Bard, Gerstlauer, Valvano, Yerraballi

Stack Usage Stack memory allocation Rules for stack use
Stack should always be balanced, i.e. functions should have an equal number of pushes and pops Stack accesses (push or pop) should not be performed outside the allocated area Stack reads and writes should not be performed within the free area Bard, Gerstlauer, Valvano, Yerraballi

Functions Bard, Gerstlauer, Valvano, Yerraballi

Subroutines One function calls another, so LR must be saved POP {PC}
; Divide ; find the unsigned quotient and remainder ; Inputs: dividend in R0 ; divisor in R1 ; Outputs: quotient in R2 ; remainder in R3 ;dividend = divisor*quotient + remainder Divide UDIV R2,R0,R1 ;R2=R0/R1,R2 is quotient MUL R3,R2,R1 ;R3=(R0/R1)*R1 SUB R3,R0,R3 ;R3=R0%R1, ;R3 is remainder of R0/R1 BX LR ;return ALIGN END ; Rand ; Return R0=a random number between ; 1 and 100. Call Random and then divide ; the generated number by 100 ; return the remainder+1 Rand100 PUSH {LR} ; SAVE Link BL Random ;R0 is a 32-bit random number LDR R1,=100 BL Divide ADD R0,R3,#1 POP {LR} ;Restore Link back BX LR POP {PC} One function calls another, so LR must be saved Bard, Gerstlauer, Valvano, Yerraballi

Reset, Subroutines and Stack
A Reset occurs immediately after power is applied and when the reset signal is asserted (Reset button pressed) The Stack Pointer, SP (R13) is initialized at Reset to the 32-bit value at location 0 (Default: 0x ) The Program Counter, PC (R15) is initialized at Reset to the 32-bit value at location 4 (Reset Vector) (Default: 0x ) The Link Register (R14) is initialized at Reset to 0xFFFFFFFF Thumb bit is set at Reset Processor automatically saves return address in LR when a subroutine call is invoked. User can push and pull multiple registers on or from the Stack at subroutine entry and before subroutine return. Bard, Gerstlauer, Valvano, Yerraballi

Introduction to C C is a high-level language
Abstracts hardware Expressive Readable Analyzable C is a procedural language The programmer explicitly specifies steps Program composed of procedures Functions/subroutines C is compiled (not interpreted) Code is analyzed as a whole (not line by line) Ramesh Yerraballi, Jon Valvano, Bill Bard, Andreas Gerstlauer Bard, Gerstlauer, Valvano, Yerraballi 50

Why C? C is popular C influenced many languages
C is considered close-to-machine Language of choice when careful coordination and control is required Straightforward behavior (typically) Typically used to program low-level software (with some assembly) Drivers, runtime systems, operating systems, schedulers, … Bard, Gerstlauer, Valvano, Yerraballi 51

Introduction to C Program structure Variables and types Statements
Subroutines and functions Variables and types Statements Preprocessor DEMO Bard, Gerstlauer, Valvano, Yerraballi 52

C Program (demo) Preprocessor directives Variables Functions Statements Expressions Names Operators Comments Syntax Bard, Gerstlauer, Valvano, Yerraballi 53

Important Notes C comes with a lot of “built-in” functions
printf() is one good example Definition included in header files #include<header_file.h> C has one special function called main() This is where execution starts (reset vector) C development process Compiler translates C code into assembly code Assembler (e.g. built into uVision4) translates assembly code into object code Object code runs on machine Bard, Gerstlauer, Valvano, Yerraballi 54

Lecture 3: Debugging, Arithmetic Operations, More I/O, Switch and LED interfacing Bard, Gerstlauer, Valvano, Yerraballi

Agenda Recap Outline GPIO Logic and Shift Operations Addressing Modes
Subroutines and the Stack Introduction to C Outline Debugging Arithmetic Operations Random Number Generator example Digital Logic GPIO TM4C123/LM4F120 Specifics Switch and LED interfacing Bard, Gerstlauer, Valvano, Yerraballi

Debugging Aka: Testing, Diagnostics, Verification Debugging Actions
Functional debugging, input/output values Performance debugging, input/output values with time Tracing, measure sequence of operations Profiling, measure percentage for tasks, time relationship between tasks Performance measurement, how fast it executes Optimization, make tradeoffs for overall good improve speed, improve accuracy, reduce memory, reduce power, reduce size, reduce cost Debugging principles Control and observability Can’t see everything; need to be smart when debugging Bard, Gerstlauer, Valvano, Yerraballi 57

Debugging Intrusiveness
Intrusive Debugging degree of perturbation caused by the debugging itself how much the debugging slows down execution Non-intrusive Debugging characteristic or quality of a debugger allows system to operate as if debugger did not exist e.g., logic analyzer, ICE, BDM Minimally intrusive negligible effect on the system being debugged e.g., dumps(ScanPoint) and monitors Highly intrusive print statements, breakpoints and single-stepping Minimally intrusive Dumps execute faster (<1us) compared to print statements (10ms) Bard, Gerstlauer, Valvano, Yerraballi 58

Debugging Aids in Keil Interface Breakpoints Registers including xPSR
Memory and Watch Windows Logic Analyzer, GPIO Panel Single Step, StepOver, StepOut, Run, Run to Cursor Watching Variables in Assembly EXPORT VarName[DATA,SIZE=4] Command Interface (Advanced but useful) WS 1, `VarName,0x10 LA (PORTD & 0x02)>>1 Commands given: 1: WS 1, `VarName,0x10 Puts the variable called VarName in the first watch window 2: LA (PORTD & 0x02)>>1 Puts port D pin 2 in logic anlayzer Bard, Gerstlauer, Valvano, Yerraballi 59

… Debugging Instrumentation: Code we add to the system that aids in debugging E.g., print statements Good practice: Define instruments with specific pattern in their names Use instruments that test a run time global flag leaves a permanent copy of the debugging code causing it to suffer a runtime overhead simplifies “on-site” customer support. Use conditional compilation (or conditional assembly) Keil supports conditional assembly Easy to remove all instruments Visualization: How the debugging information is displayed Black box testing Control inputs, observe outputs White box testing 0) pick the most likely place of failure 1) desk check: conceive of what you expect will happen at each step 2) breakpoint at the start of the place 3) single step (or step over) 4) compare what actually happened to what you wanted to have happen Bard, Gerstlauer, Valvano, Yerraballi 60

ARM ISA : ADD, SUB and CMP ARITHMETIC INSTRUCTIONS
ADD{S} {Rd,} Rn, <op2> ;Rd = Rn + op2 ADD{S} {Rd,} Rn, #im12 ;Rd = Rn + im12 SUB{S} {Rd,} Rn, <op2> ;Rd = Rn - op2 SUB{S} {Rd,} Rn, #im ;Rd = Rn - im12 RSB{S} {Rd,} Rn, <op2> ;Rd = op2 - Rn RSB{S} {Rd,} Rn, #im12 ;Rd = im12 - Rn CMP Rn, <op2> ;Rn - op2 CMN Rn, <op2> ;Rn - (-op2) ‘S’ variants: set condition codes (default: not set) Addition C bit set if unsigned overflow V bit set if signed overflow Subtraction C bit clear if unsigned overflow V bit set if signed overflow Bard, Gerstlauer, Valvano, Yerraballi

ARM ISA : Multiply and Divide
32-BIT MULTIPLY/DIVIDE INSTRUCTIONS MUL{S} {Rd,} Rn, Rm ;Rd = Rn * Rm MLA Rd, Rn, Rm, Ra ;Rd = Ra + Rn*Rm MLS Rd, Rn, Rm, Ra ;Rd = Ra - Rn*Rm UDIV {Rd,} Rn, Rm ;Rd = Rn/Rm unsigned SDIV {Rd,} Rn, Rm ;Rd = Rn/Rm signed MULS sets N and Z, but not C and V. Multiplication does not set C,V bits Bard, Gerstlauer, Valvano, Yerraballi

Random Number Generator
;Program demonstrates Arithmetic operations ; ADD, SUB, MUL and IDIV ; LR loss when sub calls sub - Solution Seed EQU THUMB AREA DATA, ALIGN=2 EXPORT M [DATA,SIZE=4] M SPACE 4 ALIGN AREA |.text|, CODE, READONLY, ALIGN=2 EXPORT Start ; Need this to be able to watch RAM ; Variable M (in Assembly only) Start LDR R2,=M ; R2 points to M LDR R0,=Seed ; Initial seed STR R0,[R2] ; M=Seed loop BL Random ; R0 has rand number B loop ; Random ; Return R0= 32-bit random number ; Linear congruential generator ; from Numerical Recipes by Press et al. Random LDR R2,=M ; R2 points to M LDR R0,[R2] ; R0=M LDR R1,= MUL R0,R0,R1 ; R0 = *M LDR R1,= ADD R0,R1 ; *M STR R0,[R2] ; store M BX LR Global variable M How it is defined How it is written How it is read Function Random How it is called How it returns Bard, Gerstlauer, Valvano, Yerraballi

Bus Driver Tristate Gate Bard, Gerstlauer, Valvano, Yerraballi

Open Collector Used to control current to LED
Low allows current to flow to ground HiZ prevents current from flowing Bard, Gerstlauer, Valvano, Yerraballi

Input/Output: TM4C123 6 General-Purpose I/O (GPIO) ports:
Four 8-bit ports (A, B, C, D) One 6-bit port (E) One 5-bit port (F) Bard, Gerstlauer, Valvano, Yerraballi 66

TM4C123 I/O Pins I/O Pin Characteristics
Can be employed as an n-bit parallel interface Pins also provide alternative functions: UART Universal asynchronous receiver/transmitter SSI Synchronous serial interface I2C Inter-integrated circuit Timer Periodic interrupts, input capture, and output compare PWM Pulse width modulation ADC Analog to digital converter, measure analog signals Analog Compare two analog signals Comparator QEI Quadrature encoder interface USB Universal serial bus Ethernet High speed network CAN Controller area network Set AFSEL to 0 Set AFSEL to 1 Bard, Gerstlauer, Valvano, Yerraballi

TM4C123 LaunchPad I/O Pins

TM4C123 I/O registers Four 8-bit ports (A, B, C, D) One 6-bit port (E)
One 5-bit port (F) PA1-0 to COM port PC3-0 to debugger PD5-4 to USB device Bard, Gerstlauer, Valvano, Yerraballi 69

Switch Configuration positive – pressed = ‘1’ negative – pressed = ‘0’

Switch Configuration Positive Logic t Negative Logic s
– pressed, 0V, false – not pressed, 3.3V, true Positive Logic t – pressed, 3.3V, true – not pressed, 0V, false Bard, Gerstlauer, Valvano, Yerraballi

LED Interfacing LED current v. voltage Brightness = power = V*I
anode (+) cathode (1) “big voltage connects to big pin” Bard, Gerstlauer, Valvano, Yerraballi

LED Configuration Bard, Gerstlauer, Valvano, Yerraballi

LED Interfacing R = (3V – 1.5)/0.001 = 1.5 kOhm R = (5.0-2-0.5)/0.01
LED current < 8 ma LED current > 8 ma LED may contain several diodes in series Bard, Gerstlauer, Valvano, Yerraballi

LaunchPad Switches and LEDs
The switches on the LaunchPad Negative logic Require internal pull-up (set bits in PUR) The PF3-1 LEDs are positive logic Bard, Gerstlauer, Valvano, Yerraballi

Initialization Ritual
Initialization (executed once at beginning) Turn on Port F clock in SYSCTL_RCGC2_R Wait two bus cycles (two NOP) Unlock PF0 (PD7 also needs unlocking) Clear AMSEL to disable analog Clear PCTL to select GPIO Set DIR to 0 for input, 1 for output Clear AFSEL bits to 0 to select regular I/O Set PUE bits to 1 to enable internal pull-up Set DEN bits to 1 to enable data pins Input from switches, output to LED Read/write GPIO_PORTF_DATA_R Prog 4.1, show PortF_Init function in InputOutput_xxxasm Bard, Gerstlauer, Valvano, Yerraballi 76

I/O Port Bit-Specific I/O Port bit-specific addressing is used to access port data register Define address offset as 4*2b, where b is the selected bit position 256 possible bit combinations (0-8) Add offsets for each bit selected to base address for the port Example: PF4 and PF0 Port F = 0x 0x x0004+0x0040 = 0x Provides friendly and atomic access to port pins Show PortF_Input2 function in InputOutput_xxxasm Bard, Gerstlauer, Valvano, Yerraballi

Lecture 4: Arithmetic overflow, Branches, Control Structures, Abstraction & Refinement Bard, Gerstlauer, Valvano, Yerraballi

Agenda Recap Outline Debugging I/O C Programming Arithmetic Overflow
Switch and LED interfacing C Programming Random number generator, NOT gate in Keil Outline Arithmetic Overflow Conditional Branches Conditional and Iterative Statements if, while, for (In assembly and C) Abstraction & Refinement Device Driver 1) Introduction to C Assembly-C Side by side main program global variable signed-unsigned bits I/O port I/O Logical-arithmetic expressions Bard, Gerstlauer, Valvano, Yerraballi

Condition Codes Bit Name Meaning after add or sub N negative result is negative Z zero result is zero V overflow signed overflow C carry unsigned overflow C set after an unsigned addition if the answer is wrong C clear after an unsigned subtract if the answer is wrong V set after a signed addition or subtraction if the answer is wrong Bard, Gerstlauer, Valvano, Yerraballi

8-bit unsigned number wheel
224+64 96+64 C bit Set C bit Cleared The carry bit, C, is set after an unsigned addition when the result is incorrect. The carry bit, C, is clear after an unsigned subtraction when the result is incorrect. Bard, Gerstlauer, Valvano, Yerraballi

8-bit unsigned number wheel
32-64 160-64 C bit Set C bit Cleared The carry bit, C, is set after an unsigned addition when the result is incorrect. The carry bit, C, is clear after an unsigned subtraction when the result is incorrect. Bard, Gerstlauer, Valvano, Yerraballi

Trick (unsigned) Convert both numbers to unsigned
Perform addition or subtraction Does the result fit as an unsigned? No -> addition C=1, subtraction C=0 Yes -> addition C=0, subtraction C=1 For example: = 260, C = 1 and the actual answer is = 4 Bard, Gerstlauer, Valvano, Yerraballi

8-bit signed number wheel
96+64 -32+64 V bit Cleared V bit Set The overflow bit, V, is set after a signed addition or subtraction when the result is incorrect. Bard, Gerstlauer, Valvano, Yerraballi

8-bit signed number wheel
-96-64 32-64 V bit Cleared V bit Set The overflow bit, V, is normally set when we cross over from 127 to -128 while adding or cross over from -128 to 127 while subtracting. Bard, Gerstlauer, Valvano, Yerraballi

Trick (signed) Convert both numbers to signed
Perform addition or subtraction Does the result fit as a signed? No -> V=1 Yes -> V=0 8-bit Examples: 10 – 5 = 5, V=0 -100 – 100 = -200, V=1 Bard, Gerstlauer, Valvano, Yerraballi

Addition Summary N bit is set Z bit is set if result is zero
Let the 32-bit result R be the result of the 32-bit addition X+Y. N bit is set if unsigned result is above or if signed result is negative. N = R31 Z bit is set if result is zero V bit is set after a signed addition if result is incorrect C bit is set after an unsigned addition if result is incorrect Bard, Gerstlauer, Valvano, Yerraballi

Subtraction Summary N bit is set Z bit is set if result is zero
Let the 32-bit result R be the result of the 32-bit subtraction X-Y. N bit is set if unsigned result is above or if signed result is negative. N = R31 Z bit is set if result is zero V bit is set after a signed subtraction if result is incorrect C bit is clear after an unsigned subtraction if result is incorrect Bard, Gerstlauer, Valvano, Yerraballi

Trick Question Answer = 159 NZVC = 1010
When the subtraction (32 – 129) is performed in an 8-bit system what is the result and the status of the NZVC bits? Answer = 159 NZVC = 1010 This is trick question because can be done as unsigned 8-bit arithmetic (C=0 indicating the subtraction causes an error) but when you dos signed 8-bit arithmetic you realize that, valid 8-bit signed numbers range from -128 to So ,129 which is the binary pattern is really -127 as an 8-bit signed number. So the actual arithmetic being performed is 32-(-127) which is 159, which is outside the range of valid 8-bit signed numbers, therefore setting the V bit. So, the lesson is “garbage in garbage out”. Make sure your inputs are “valid”, otherwise the outputs can be unpredictable. Bard, Gerstlauer, Valvano, Yerraballi

Unsigned Promotion Promotion involves increasing the precision of the input numbers, and performing the operation at that higher precision Then truncate the result back to the original precision Decimal 8-bit bit , ,0000,0000,0000,0000,0000,1110,0000 , ,0000,0000,0000,0000,0000,0100,0000 , ,0000,0000,0000,0000,0001,0010,0000 signed and unsigned promotion in C and assembly Bard, Gerstlauer, Valvano, Yerraballi

Unsigned Ceiling and Floor

Signed Promotion To promote a signed number, we duplicate the sign bit
Decimal 8-bit bit , ,1111,1111,1111,1111,1111,1010,0000 , ,0000,0000,0000,0000,0000,0100,0000 , ,1111,1111,1111,1111,1111,0110,0000 Otherwise known as sign extension (SEXT opcode) Bard, Gerstlauer, Valvano, Yerraballi

Signed Ceiling and Floor

Conditional Branch Instructions
Unsigned conditional branch follow SUBS CMN or CMP BLO target ; Branch if unsigned less than (if C=0, same as BCC) BLS target ; Branch if unsigned less than or equal to (if C=0 or Z=1) BHS target ; Branch if unsigned greater than or equal to (if C=1, same as BCS) BHI target ; Branch if unsigned greater than (if C=1 and Z=0) CMP R0,R1 R0<R1 BLO R0≥R1 target Next instruction Bard, Gerstlauer, Valvano, Yerraballi

Conditional Branch Instructions
Signed conditional branch follow SUBS CMN or CMP BLT target ; if signed less than (if (~N&V | N&~V)=1 if N≠V) BGE target ; if signed greater than or equal to (if (~N&V | N&~V)=0 if N=V) BGT target ; if signed greater than (if (Z | ~N&V | N&~V)=0 if Z=0 and N=V) BLE target ; if signed less than or equal to (if (Z | ~N&V | N&~V)=1 if Z=1 and N≠V) CMP R0,R1 R0<R1 BLT R0≥R1 target Next instruction Bard, Gerstlauer, Valvano, Yerraballi

Equality Test Program 5.1. Conditional structures that test for equality. Bard, Gerstlauer, Valvano, Yerraballi

Unsigned Conditional Structures
Program 5.2. Unsigned conditional structures. Bard, Gerstlauer, Valvano, Yerraballi

Signed Conditional Structures
Program 5.4. Signed conditional structures. Bard, Gerstlauer, Valvano, Yerraballi

If-then-else Bard, Gerstlauer, Valvano, Yerraballi

While Loops LDR R4, =G1 ; R4 -> G1 unsigned long G1,G2;
loop LDR R0, [R5] ; R0 = G2 LDR R1, [R4] ; R1 = G1 CMP R0, R1 ; is G2 <= G1? BLS next ; if so, skip to next BL Body ; body of the loop B loop next unsigned long G1,G2; while(G2 > G1){ Body(); } Bard, Gerstlauer, Valvano, Yerraballi

For Loops Bard, Gerstlauer, Valvano, Yerraballi

For Loops Count up Count down MOV R4, #0 ; R4 = 0
loop CMP R4, #100 ; index >= 100? BHS done ; if so, skip to done BL Process ; process function* ADD R4, R4, #1 ; R4 = R4 + 1 B loop done for(i=0; i<100; i++){ Process(); } Count up MOV R4, #100 ; R4 = 0 loop BL Process ; process function SUBS R4, R4, #1 ; R4 = R4 - 1 BNE loop done for(i=100; i!=0; i--){ Process(); } Count down Bard, Gerstlauer, Valvano, Yerraballi

System Design What does being in a state mean? List state parameters
What is the starting state of the system? Define the initial state What information do we need to collect? List the input data What information do we need to generate? List the output data How do we move from one state to another? Actions we could do What is the desired ending state? Define the ultimate goal Bard, Gerstlauer, Valvano, Yerraballi

System Design Successive Refinement Stepwise Refinement
Systematic Decomposition Bard, Gerstlauer, Valvano, Yerraballi

System Design Start with a task and decompose the task into a set of simpler subtasks Subtasks are decomposed into even simpler sub-subtasks Each subtask is simpler than the task itself Make design decisions document decisions and subtask requirements Ultimately, subtask is so simple, it can be converted to software Bard, Gerstlauer, Valvano, Yerraballi

System Design Four building blocks: “do A then do B” → sequential
“do A and B in either order” → sequential (parallel) “if A, then do B” → conditional “for each A, do B” → iterative “do A until B” → iterative “repeat A over & over forever” → iterative (condition always true) “on external event do B” → interrupt “every t msec do B” → interrupt Bard, Gerstlauer, Valvano, Yerraballi

Successive Refinement

Successive Refinement
Successive refinement example for iterative approach Bard, Gerstlauer, Valvano, Yerraballi

Abstraction - Device Driver
Abstraction allows us to modularize our code and give us the option to expose what we want users to see and hide what we don’t want them to see. A Device Driver is a good example where abstraction is used to expose public routines that we want users of the driver to call and use private routines to hide driver internals from the user (more on private routines later) LED Driver (PE0) LED_Init A user simply has to know what a routine expects and what it returns in order to call it (calling convention). Internals do not matter to caller LED_Off LED_On LED_Toggle Bard, Gerstlauer, Valvano, Yerraballi

Port E LED Abstraction PE0 EQU 0x ;bit-specific address Port E bit 0 LED_Init LDR R1, =SYSCTL_RCGC2_R ; R1 -> SYSCTL_RCGC2_R LDR R0, [R1] ; previous value ORR R0, R0, #0x ; activate clock for Port E STR R0, [R1] NOP NOP ; allow time to finish activating LDR R1, =GPIO_PORTE_DIR_R ; R1 -> GPIO_PORTE_DIR_R ORR R0, R0, #0x ; PE0 output STR R0, [R1] ; set direction register LDR R1, =GPIO_PORTE_AFSEL_R ; R1 -> GPIO_PORTE_AFSEL_R BIC R0, R0, #0x ; disable alt funct STR R0, [R1] ; set alternate function register LDR R1, =GPIO_PORTE_DEN_R ; R1 -> GPIO_PORTE_DEN_R ORR R0, R0, #0x ; enable PE0 digital port STR R0, [R1] ; set digital enable register BX LR Program 4.3. Software interface for an LED on PE0 (SSR_xxx.zip). Bard, Gerstlauer, Valvano, Yerraballi

Port E LED Abstraction LED_Off LDR R1, =PE ; R1 is 0x MOV R0, #0 STR R0, [R1] ; affect just PE0 BX LR LED_On MOV R0, #1 LED_Toggle LDR R0, [R1] ; previous value EOR R0, R0, # ; flip bit 0 Program 4.3. Software interface for an LED on PE0 (SSR_xxx.zip). Bard, Gerstlauer, Valvano, Yerraballi

Lecture 5:Subroutines and Parameter passing, Pointers, Arrays and Strings, Functional Debugging Bard, Gerstlauer, Valvano, Yerraballi

Agenda Recap Outline Branches and Arithmetic overflow
Signed (V) vs. Unsigned (C) Control Structures if, if-else, while, do-while, for Signed: B{LT,GE,GT,LE}; LDRSB, LDRSH Unsigned: B{LO,HS,HI,LS}; LDRB, LDRH Outline Subroutines and Parameter Passing Indexed Addressing and Pointers Data Structures: Arrays, Strings Functional Debugging Bard, Gerstlauer, Valvano, Yerraballi

Registers to pass parameters
Subroutine 3) Sees the inputs in registers 4) Performs the action of the subroutine 5) Places the outputs in registers High level program Sets Registers to contain inputs Calls subroutine 6) Registers contain outputs Bard, Gerstlauer, Valvano, Yerraballi

Stack to pass parameters
Subroutine 3) Sees the inputs on stack (pops) 4) Performs the action of the subroutine 5) Pushes outputs on the stack High level program Pushes inputs on the Stack Calls subroutine 6) Stack contain outputs (pop) 7) Balance stack Bard, Gerstlauer, Valvano, Yerraballi

Assembly Parameter Passing
Parameters passed using registers/stack Parameter passing need not be done using only registers or only stack Some inputs could come in registers and some on stack and outputs could be returned in registers and some on the stack Calling Convention Application Binary Interface (ABI) ARM: use registers for first 4 parameters, use stack beyond, return using R0 Keep in mind that you may want your assembly subroutine to someday be callable from C or callable from someone else’s software Bard, Gerstlauer, Valvano, Yerraballi

ARM Arch. Procedure Call Standard (AAPCS)
ABI standard for all ARM architectures Use registers R0, R1, R2, and R3 to pass the first four input parameters (in order) into any function, C or assembly. We place the return parameter in Register R0. Functions can freely modify registers R0–R3 and R12. If a function needs to use R4 through R11, it is necessary to push the current register value onto the stack, use the register, and then pop the old value off the stack before returning. Bard, Gerstlauer, Valvano, Yerraballi

Parameter-Passing: Registers
Caller ;--call a subroutine that ;uses registers for parameter passing MOV R0,#7 MOV R1,#3 BL Exp ;; R2 becomes 7^3 = 343 (0x157) Callee ; Exp ; Input: R0 and R1 have inputs XX an YY ; Output: R2 has the result XX raised to YY ; Comments: R1 and R2 and non-negative ; Destroys input R1 XX RN 0 YY RN 1 Pow RN 2 Exp ADDS XX,#0 BEQ Zero ADDS YY,#0 ; check if YY is zero BEQ One MOV pow, #1 ; Initial product is 1 More MUL pow,XX ; multiply product with XX ADDS YY,#-1 ; Decrement YY BNE More B Retn ; Done, so return Zero MOV pow,#0 ; XX is 0 so result is 0 B Retn One MOV pow,#1 ; YY is 0 so result is 1 Retn BX LR Call by value Suggest changes to make it AAPCS Return by value Bard, Gerstlauer, Valvano, Yerraballi

Parameter-Passing: Stack
Caller ; call a subroutine that ; uses stack for parameter passing MOV R0,#12 MOV R1,#5 MOV R2,#22 MOV R3,#7 MOV R4,#18 PUSH {R0-R4} ; Stack has 12,5,22,7 and 18 ; (with 12 on top) BL Max5 ; Call Max5 to find the maximum ;of the five numbers POP {R5} ;; R5 has the max element (22) Callee ; Max ; Input: 5 signed numbers pushed on the stack ; Output: put only the maximum number on the stack ; Comments: The input numbers are removed from stack numM RN 1 ; current number max RN 2 ; maximum so far count RN 0 ; how many elements Max5 POP {max} ; get top element (top of stack) ; store it in max MOV count,#4 ; 4 more to go Again POP {numM} ; get next element CMP numM,max BLT Next MOV max, numM ; new numM is the max Next ADDS count,#-1 ; one more checked BNE Again PUSH {max} ; found max so push it on stack BX LR Not AAPCS because we totally bypassed registers as a means of passing parameters Call by value Return by value Flexible style, but not AAPCS Bard, Gerstlauer, Valvano, Yerraballi

Parameter-Passing: Stack & Regs
Caller ;------call a subroutine that uses ;both stack and registers for ;parameter passing MOV R0,#6 ; R0 elem count MOV R1,#-14 MOV R2,#5 MOV R3,#32 MOV R4,#-7 MOV R5,#0 MOV R6,#-5 PUSH {R4-R6} ; rest on stack ; R0 has element count ; R1-R3 have first 3 elements; ; remaining on Stack BL MinMax ;; R0 has -14 and R1 has 32 ;; upon return Callee ; MinMax ; Input: N numbers reg+stack; N passed in R0 ; Output: Return in R0 the min and R1 the max ; Comments: The input numbers are removed from stack numMM RN 3; hold the current number in numMM max RN ; hold maximum so far in max min RN 2 N RN ; how many elements MinMax PUSH {R1-R3} ; put all elements on stack CMP N,#0 ; if N is zero nothing to do BEQ DoneMM POP {min} ; pop top and set it MOV max,min ; as the current min and max loop ADDS N,# ; decrement and check BEQ DoneMM POP {numMM} CMP numMM,max BLT Chkmin MOV max,numMM ; new num is the max Chkmin CMP numMM,min BGT NextMM MOV min,numMM ; new num is the min NextMM B loop DoneMM MOV R0,min ; R0 has min BX LR Not AAPCS because we are returning two outputs. Can fix by putting min and max at two consecutive locations in memory and returning the address of the first in R0 Not AAPCS Bard, Gerstlauer, Valvano, Yerraballi

Pointers Pointers are addresses that refer to objects
Objects may be data, functions or other pointers If a register or memory location contains an address we say it points into memory Use of indexed addressing mode

{ Data Structures Pointers are the basis for data structures
Organization of data Functions to facilitate access Data structure Bard, Gerstlauer, Valvano, Yerraballi

{ Arrays Random access Sequential access An array
equal precision and allows random access. The precision is the size of each element. (n) The length is the number of elements (fixed or variable). The origin is the index of the first element. zero-origin indexing. { Data in consecutive memory Access: Buffer[i] long Buffer[100] Bard, Gerstlauer, Valvano, Yerraballi

Array Declaration In assembly In C Length of the array?
A SPACE 400 Prime DCW 1,2,3,5,7,11,13 In C unsigned long A[100]; unsigned short Prime[] = {1,2,3,5,7,11,13}; Length of the array? One simple mechanism saves the length of the array as the first element In C: const char Data[5]={4,0x05,0x06,0x0A,0x09}; const short Powers[6]={5,1,10,100,1000,10000}; const long Filter[5]= {4,0xAABBCCDD,0x00,0xFFFFFFFF,-0x01} In assembly: Data DCB 4,0x05,0x06,0x0A,0x09 Powers DCW 5,1,10,100,1000,10000 Filter DCD 4,0xAABBCCDD, 0x00 DCD 0xFFFFFFFF,-0x01 With the keyword const the C compiler forces the array to be placed in ROM. Split declaration on multiple lines if needed Bard, Gerstlauer, Valvano, Yerraballi

… Arrays Length of the Array:
Alternative mechanism stores a special termination code as the last element. Bard, Gerstlauer, Valvano, Yerraballi

Array Access In C d = Prime[4]; In assembly LDR R0,=Prime
In general, let n be the precision of a zero-origin indexed array in elements. n=1 (8-bit elements) n=2 (16-bit elements) n=4 (32-bit elements) If I is the index and Base is the base address of the array, then the address of the element at I is Base+n*I In C d = Prime[4]; In assembly LDR R0,=Prime LDRH R1,[R0,#8] In C, the program only gives the index I The compiler knows about base data type and hence element size n of the array. Compiler computes the correct offset n*I automatically In assembly, offset computations need to be done by the programmer Bard, Gerstlauer, Valvano, Yerraballi

Array Access Indexed access Pointer access In C In assembly In C
unsigned i; sum = 0; for(i=0; i<7; i++) { sum += Prime[i]; } In assembly LDR R0,=Prime MOV R1,#0 ; ofs = 0 MOV R3,#0 ; sum = 0 lp LDR R2,[R0,R1] ;Prime[i] ADD R3,R3,R2 ; sum ADD R1,R1,#2 ; ofs += 2 CMP R1,#14 ; ofs <= 14? BLO lp Pointer access In C unsigned short *p; sum = 0; for(p = Prime; p != &Prime[7]; p++) { sum += *p; } In assembly LDR R0,=Prime ; p = Prime ADD R1,R0,#14 ; &Prime[7] MOV R3,#0 ; sum = 0 lp LDR R2,[R0] ; *p ADD R3,R3,R2 ; sum += .. ADD R0,R0,#2 ; p++ CMP R0,R1 BNE lp In C, Prime is the same as &Prime (“address of Prime”), where both evaluate to the same result as &(Prime[0]), i.e. the address of the first array element. In C, additions of integers to pointers are possible. The result of such an expression is again a pointer, where this so-called pointer arithmetic is always relative to the size of the pointer’s base type. In assembly, the programmer has to ensure that pointers are incremented by the correct number of bytes.

Example 6.2 const unsigned long Powers[10] =
Statement: Design an exponential function, y = 10x, with a 32-bit output. Solution: Since the output is less than 4,294,967,295, the input must be between 0 and 9. One simple solution is to employ a constant word array, as shown below. Each element is 32 bits. In assembly, we define a word constant using DCD, making sure in exists in ROM. Assembly AREA |.text| Scores DCW 75,87,89,92,90 C const unsigned short Scores[5] = { }; AREA data Grades SPACE 10 unsigned short Grades[5]; Curve ADD R0,R0,#5 CMP R0,#100 BLS ok MOV R0,#100 ok BX LR unsigned short Curve(unsigned short in){unsigned short out; out = in+5; if(out>100) out=100; return out; } LDR R3,=Grades LDR R1,=Scores MOV R2,#0 loop LDR R0,[R1,R2] BL Curve STR R0,[R3,R2] ADD R2,#2 CMP R2,#10 BLO loop for(i=0; i<5; i++){ Grades[i] = Curve(Scores[i]); const unsigned long Powers[10] = {1,10,100,1000,10000,100000, , , , }; Bard, Gerstlauer, Valvano, Yerraballi

…Solution Base + Offset AREA |.text|,CODE,READONLY,ALIGN=2
const unsigned long Powers[10] ={1,10,100,1000,10000, 100000, , , , }; unsigned long power(unsigned long x){ return Powers[x]; } Assembly AREA |.text|,CODE,READONLY,ALIGN=2 Powers DCD 1, 10, 100, 1000, 10000 DCD , , DCD , ;------power---- ; Input: R0=x ; Output: R0=10^x power LSL R0, R0, #2 ; x = x*4 LDR R1, =Powers ; R1= &Powers LDR R0, [R1, R0] ; y=Powers[x] BX LR Base + Offset Bard, Gerstlauer, Valvano, Yerraballi

Strings Problem: Write software to output an ASCII string to an output device. Solution: Because the length of the string may be too long to place all the ASCII characters into the registers at the same time, call by reference parameter passing will be used. With call by reference, a pointer to the string will be passed. The function OutString, will output the string data to the output device. The function OutChar will be developed later. For now all we need to know is that it outputs a single ASCII character to the serial port. Bard, Gerstlauer, Valvano, Yerraballi

…Solution Call by reference Hello DCB "Hello world\n\r",0
;Input: R0 points to string OutString PUSH {R4, LR} MOV R4, R0 loop LDRB R0, [R4] ADD R4, #1 ;next CMP R0, #0 ;done? BEQ done ;0 sentinel BL OutChar ;print char B loop done POP {R4, PC} Start LDR R0,=Hello BL OutString const char Hello[]= "Hello world\n\r"; void OutString(unsigned char *pt){ unsigned char letter; while(letter = (*pt++)){ UART_OutChar(letter); } void main(void){ OutString("Hello World"); Call by reference Bard, Gerstlauer, Valvano, Yerraballi

Functional Debugging Cnt = 0; LDR R0,=Cnt MOV R1,#0 STR R1,[R0]
Cnt will be used to index into the buffers Cnt must be set to index the first element, before the debugging begins. #define SIZE 20 unsigned char HappyBuf[SIZE]; unsigned char SadBuf[SIZE]; unsigned long Cnt; SIZE EQU 20 HappyBuf SPACE SIZE SadBuf SPACE SIZE Cnt SPACE 4 Instrumentation: dump into array without filtering Assume happy and sad are strategic 8-bit variables. Bard, Gerstlauer, Valvano, Yerraballi

… Functional Debugging
Next, you add BL Save statements at strategic places within the system. Use the debugger to display the results after program is done void Save(void){ if(Cnt < SIZE){ HappyBuf[Cnt] = happy; SadBuf[Cnt] = sad; Cnt++; } Save PUSH {R0-R3,LR} LDR R0,=Cnt ;R0 = &Cnt LDR R1,[R0] ;R1 = Cnt CMP R1,#SIZE BHS done ;full? LDR R3,=Happy LDRB R3,[R3] ;R3 is happy LDR R2,=HappyBuf STRB R3,[R2,R1] ;save happy LDR R3,=Sad LDRB R3,[R3] ;R3 is sad LDR R2,=SadBuf STRB R3,[R2,R1] ;save sad ADD R1,#1 STR R1,[R0] ;save Cnt done POP {R0-R3,PC} The debugging instrument saves the strategic variables happy and sad into respective Buffers Discuss nonintrusive, minimally intrusive and highly intrusive Logic analyzer Dump data/time into buffer Printf Embedded systems (function values, time important) Instrument Lab 1, does the LED flash at 1ms Quantify intrusiveness at time to execute (count bus cycles) Conditional dump Debugging instruments save/restore all registers Bard, Gerstlauer, Valvano, Yerraballi

Lab 4 preparation 0) Watch Video 9.1 in ebook chapter 9
1) Read and watch section 9.5 in the ebook 2) Watch Videos 10.1 and in ebook chapter 10 3) Read textbook sections 4.3 and 4.4, you will use assembly code from book Program 4.7 Bard, Gerstlauer, Valvano, Yerraballi

Lecture 6: SysTick Timer, Exam 1 Review

Agenda Recap Outline Subroutines and Parameter Passing
AAPCS Convention Indexed Addressing and Pointers In C: Address of (&), Pointer to (*) Data Structures: Arrays, Strings Length: hardcoded vs. embedded vs. sentinel Array access: indexed vs. pointer arithmetic Functional Debugging Outline Exam 1 Review SysTick Timer

Exam 1 Syllabus Lectures 1, 2, 3, 4, 5 (till slide 10) Labs 1, 2, 3
Homework 0, 1, 2, 3, 4 Chapters 1-5 from text Some sections skipped (see HW4) Look at slides for reference Chapter 1, 2, 3 from Zyante online book Worksheets 1, 2, 3, 4, 5 (no arrays)

Exam 1 Review Definitions (define in 16 words or less, choose the word, or multiple choice) volatile, nonvolatile, RAM, ROM, port static efficiency, dynamic efficiency structured program, call graph, data flow graph basis, nibble, precision, kibibyte, mebibyte signed/unsigned, overflow, ceiling and floor, drop out bus, address bus, data bus memory-mapped, I/O mapped Harvard architecture, von Neumann, pipelining ALU, D flip flop, registers device driver, CISC, RISC friendly, mask, toggle Negative logic, positive logic, tristate, open collector

Exam 1 Review Number conversions - convert one format to another
alternatives, binary bits signed decimal e.g., -56 unsigned decimal e.g., 200 binary e.g., hexadecimal e.g., 0xC8

Exam 1 Review Cortex-M4 operation & instructions
8-bit addition, subtraction Yielding result, N, Z, V, C Operation of Thumbnail instructions Components in address space Subroutine linkage Stack operations Switch and LED interfaces C Programming Declarations, expressions, control flow Conditionals and Loops No Arrays on Exam 1 Instructions: LDR STR ADD ADDS SUB SUBS MUL UDIV SDIV ASR LSR LSL AND ORR EOR BNE BEQ BLO BLS BHS BHI BGT BGE BLE BLT RAM, ROM, I/O little endian What does PUSH do? How are registers stored “low number into low memory address” What does POP do? Show all 4 switch interfaces (negative logic/positive logic, hardware/software= internal/external pullup/down) Show all 4 LED interfaces (negative/positive logic, <8mA/>8mA)

Exam1 Review Simple programs (assembly and C) create global variables
specify an I/O pin is an input specify an I/O pin is an output clear an I/O output pin to zero set an I/O output pin to one toggle an I/O output pin check if an I/O input pin is high or low add, sub, shift left, shift right, and, or, eor subroutine linkage Not on Exam Pointers in C Arrays, strings Call by reference Cycle by cycle execution

Practice Problems Book Lecture worksheets Previous year’s exams
Hardware interfacing 4.12, 4.13, 4.15 Port initialization 4.5, 4.6, 4.7, 4.10, 4.11 Software (do both in assembly and C) 4.18, 4.19, 4.20, Lab 4.3, Lab 4.5, Lab 4.6, 5.1, 5.2, 5.3, 5.4, 5.5, 5.6, 5.7, 5.8, 5.9, 5.10 Lecture worksheets Posted w/ lecture notes on class web site Previous year’s exams Homework 4 e1

SysTick Timer Timer/Counter operation
24-bit counter decrements at bus clock frequency With 80 MHz bus clock, decrements every ns Counting is from n  0 Setting n appropriately will make the counter a modulo n+1 counter. That is: next_value = (current_value-1) mod (n+1) Sequence: n,n-1,n-2,n-3… 2,1,0,n,n-1… Modulo (mod or %) operation gives the remainder: (a mod n) is the remainder when a is divided by n. When a < n, (a mod n) is simply a. When current_value reaches 0, then the next value is [(0-1)mod (n+1)] = -1 mod (n+1) = n That is the counter gets reset to max value n after it reaches 0.

SysTick Timer Initialization (4 steps)
Step1: Clear ENABLE to stop counter Step2: Specify the RELOAD value Step3: Clear the counter via NVIC_ST_CURRENT_R Step4: Set CLK_SRC=1 and specify interrupt action via INTEN in NVIC_ST_CTRL_R RELOAD value is the value to load into the counter (reset) every time it hits zero, i.e. the n value from the previous slide

SysTick Timer 24-bit Countdown Timer SysTick_Init
; disable SysTick during setup LDR R1, =NVIC_ST_CTRL_R MOV R0, # ; Clear Enable STR R0, [R1] ; set reload to maximum reload value LDR R1, =NVIC_ST_RELOAD_R LDR R0, =0x00FFFFFF; ; Specify RELOAD value STR R0, [R1] ; reload at maximum ; writing any value to CURRENT clears it LDR R1, =NVIC_ST_CURRENT_R MOV R0, #0 STR R0, [R1] ; clear counter ; enable SysTick with core clock MOV R0, #0x ; Enable but no interrupts (later) STR R0, [R1] ; ENABLE and CLK_SRC bits set BX LR 24-bit Countdown Timer You could make the Timer be a 16-bit timer by changing the RELOAD value to be 0x0000FFFF. We will see however there is no good reason to this.

SysTick Timer ;------------SysTick_Wait------------
; Time delay using busy wait. ; Input: R0 delay parameter in units of the core clock ; MHz(12.5 nsec each tick) ; Output: none ; Modifies: R1 SysTick_Wait SUB R0, R0, #1 ; delay-1 LDR R1, =NVIC_ST_RELOAD_R STR R0, [R1] ; time to wait LDR R1, =NVIC_ST_CURRENT_R STR R0, [R1] ; any value written to CURRENT clears LDR R1, =NVIC_ST_CTRL_R SysTick_Wait_loop LDR R0, [R1] ; read status ANDS R0, R0, #0x ; bit 16 is COUNT flag BEQ SysTick_Wait_loop ; repeat until flag set BX LR

SysTick Timer ;------------SysTick_Wait10ms------------
; Call this routine to wait for R0*10 ms ; Time delay using busy wait. This assumes 80 MHz clock ; Input: R0 number of times to wait 10 ms before returning ; Output: none ; Modifies: R0 DELAY10MS EQU ; clock cycles in 10 ms SysTick_Wait10ms PUSH {R4, LR} ; save R4 and LR MOVS R4, R ; R4 = R0 = remainingWaits BEQ SysTick_Wait10ms_done ; R4 == 0, done SysTick_Wait10ms_loop LDR R0, =DELAY10MS ; R0 = DELAY10MS BL SysTick_Wait ; wait 10 ms SUBS R4, R4, # ; remainingWaits-- BHI SysTick_Wait10ms_loop ; if(R4>0), wait another 10 ms SysTick_Wait10ms_done POP {R4, PC}

SysTick Timer in C #define NVIC_ST_CTRL_R(*((volatile unsigned long *)0xE000E010)) #define NVIC_ST_RELOAD_R(*((volatile unsigned long *)0xE000E014)) #define NVIC_ST_CURRENT_R(*((volatile unsigned long *)0xE000E018)) void SysTick_Init(void){ NVIC_ST_CTRL_R = 0; // 1) disable SysTick during setup NVIC_ST_RELOAD_R = 0x00FFFFFF; // 2) maximum reload value NVIC_ST_CURRENT_R = 0; // 3) any write to CURRENT clears it NVIC_ST_CTRL_R = 0x ; // 4) enable SysTick with core clock } // The delay parameter is in units of the 80 MHz core clock(12.5 ns) void SysTick_Wait(unsigned long delay){ NVIC_ST_RELOAD_R = delay-1; // number of counts NVIC_ST_CURRENT_R = 0; // any value written to CURRENT clears while((NVIC_ST_CTRL_R&0x )==0){ // wait for flag // Call this routine to wait for delay*10ms void SysTick_Wait10ms(unsigned long delay){ unsigned long i; for(i=0; i<delay; i++){ SysTick_Wait(800000); // wait 10ms Bard, Gerstlauer, Valvano, Yerraballi

Lecture 7: Phase-locked-loop, Data structures, Finite state machines, Interrupts Bard, Gerstlauer, Valvano, Yerraballi

Agenda Recap Outline Indexed Addressing and Pointers
In C: Address of (&), Pointer to (*) Data Structures: Arrays, Strings Length: hardcoded vs. embedded vs. sentinel Array access: indexed vs. pointer arithmetic Functional Debugging SysTick Timer Outline Phase Lock Loop (PLL) Data structures Finite State Machines, Linked-lists Interrupts Bard, Gerstlauer, Valvano, Yerraballi

Phase-Lock-Loop Example SYSDIV (n) values: n=4 gives 400/(4+1) = 80 MHz n=7 gives 400/(7+1) = 50MHz n=9 gives 400/(9+1) = 40MHz n=15 gives 400/(15+1) = 25MHz Internal oscillator requires minimal power but is imprecise External crystal provides stable bus clock TM4C123 is equipped with 16 MHz crystal and bus clock can be set to a maximum of 80 MHz Bard, Gerstlauer, Valvano, Yerraballi

Recap: Array access Calculate address from Base and index
Byte Base+index Halfword Base+2*index Word Base+4*index Size_N Base+N*index Access sequentially using pointers Byte pt = pt+1 Halfword pt = pt+2 Word pt = pt+4 Size_N pt = pt+N Bard, Gerstlauer, Valvano, Yerraballi

Abstraction Software abstraction Three advantages of abstraction are
Define a problem with a minimal set of basic, abstract principles / concepts Separation of concerns via interface/policy mechanisms Straightforward, mechanical path to implementation Three advantages of abstraction are it can be faster to develop it is easier to debug (prove correct) and it is easier to change Bard, Gerstlauer, Valvano, Yerraballi

Finite State Machine (FSM)
Finite State Machines (FSMs) Set of inputs, outputs, states and transitions State graph defines input/output relationship What is a state? Description of current conditions What is a state graph? Graphical interconnection between states What is a controller? Software that inputs, outputs, changes state Accesses the state graph Bard, Gerstlauer, Valvano, Yerraballi

What is a finite state machine? Inputs (sensors) Outputs (actuators) Controller State graph Bard, Gerstlauer, Valvano, Yerraballi

Moore FSM output value depends only on the current state, inputs affect the state transitions significance is being in a state Input: when to change state Output: definition of being in that state Bard, Gerstlauer, Valvano, Yerraballi

Moore FSM Execution Sequence Perform output corresponding to the current state Wait a prescribed amount of time (optional) Read inputs Change state, which depends on the input and the current state Go back to 1. and repeat Bard, Gerstlauer, Valvano, Yerraballi

Mealy FSM output value depends on input and current state inputs affect the state transitions. significance is the state transition Input: when to change state Output: how to change state Inputs: Control Outputs: Brake, Gas Bard, Gerstlauer, Valvano, Yerraballi

Mealy FSM Execution Sequence Wait a prescribed amount of time (optional) Read inputs Perform output, which depends on the input and the current state Change state, which depends on the input and the current state Go back to 1. and repeat Bard, Gerstlauer, Valvano, Yerraballi

FSM Implementation Data Structure embodies the FSM Linked Structure
multiple identically-structured nodes statically-allocated fixed-size linked structures one-to-one mapping FSM state graph and linked structure one structure for each state Linked Structure pointer (or link) to other nodes (define next states) Table structure indices to other nodes (define next states) Bard, Gerstlauer, Valvano, Yerraballi

Traffic Light Control PE1=0, PE0=0 means no cars exist on either road PE1=0, PE0=1 means there are cars on the East road PE1=1, PE0=0 means there are cars on the North road PE1=1, PE0=1 means there are cars on both roads goN, PB5-0 = makes it green on North and red on East waitN, PB5-0 = makes it yellow on North and red on East goE, PB5-0 = makes it red on North and green on East waitE, PB5-0 = makes it red on North and yellow on East Bard, Gerstlauer, Valvano, Yerraballi

Traffic Light Control Bard, Gerstlauer, Valvano, Yerraballi

Linked Data Structure In ROM OUT EQU 0 ;offset for output
WAIT EQU 4 ;offset for time (10ms) NEXT EQU 8 ;offset for next goN DCD 0x21 ;North green, East red DCD 3000 ;30 sec DCD goN,waitN,goN,waitN waitN DCD 0x22 ;North yellow, East red DCD 500 ;5 sec DCD goE,goE,goE,goE goE DCD 0x0C ;North red, East green DCD goE,goE,waitE,waitE waitE DCD 0x14 ;North red, East yellow DCD goN,goN,goN,goN In ROM Bard, Gerstlauer, Valvano, Yerraballi

FSM Engine (Moore) ; Port and timer initialization
LDR R4,=goN ; state pointer LDR R5,=SENSOR ; PortE LDR R6,=LIGHT ; PortB FSM LDR R0,[R4,#OUT] ; 1.output value STR R0,[R6] ; set lights LDR R0,[R4,#WAIT] ; 2. time delay BL SysTick_Wait10ms LDR R0,[R5] ; 3. read input LSL R0,R0,# ; offset(index): ; 4 bytes/address ADD R0,R0,#NEXT ; 8,12,16,20 LDR R4,[R4,R0] ; 4. go to next state B FSM Bard, Gerstlauer, Valvano, Yerraballi

Linked Data Structure in C
const struct State { unsigned long Out; unsigned long Time; // 10 ms units const struct State *Next[4]; }; typedef const struct State STyp; #define goN &FSM[0] #define waitN &FSM[1] #define goE &FSM[2] #define waitE &FSM[3] STyp FSM[4] = { {0x21,3000,{goN,waitN,goN,waitN}}, {0x22, 500,{goE,goE,goE,goE}}, {0x0C,3000,{goE,goE,waitE,waitE}}, {0x14, 500,{goN,goN,goN,goN}} Bard, Gerstlauer, Valvano, Yerraballi

FSM Engine in C (Moore) void main(void) { STyp *Pt; // state pointer
unsigned long Input; volatile unsigned long delay; // initialize ports and timer … Pt = goN; // start state while(1) { LIGHT = Pt->Out; // set lights SysTick_Wait10ms(Pt->Time); Input = SENSOR; // read sensors Pt = Pt->Next[Input]; } Bard, Gerstlauer, Valvano, Yerraballi

Interrupts An interrupt is the automatic transfer of software execution in response to a hardware event (trigger) that is asynchronous with current software execution. external I/O device (like a keyboard or printer) or an internal event (like an op code fault, or a periodic timer.) Occurs when the hardware needs or can service (busy to done state transition) Bard, Gerstlauer, Valvano, Yerraballi

Interrupt Processing Bard, Gerstlauer, Valvano, Yerraballi

ARM Cortex-M Interrupts
Each potential interrupt source has a separate arm bit Set for those devices from which it wishes to accept interrupts, Deactivate in those devices from which interrupts are not allowed Each potential interrupt source has a separate flag bit hardware sets the flag when it wishes to request an interrupt software clears the flag in ISR to signify it is processing the request Interrupt enable conditions in processor Global interrupt enable bit, I, in PRIMASK register Priority level, BASEPRI, of allowed interrupts (0 = all) Bard, Gerstlauer, Valvano, Yerraballi

Interrupt Conditions Four conditions must be true simultaneously for an interrupt to occur: Arm: control bit for each possible source is set Enable: interrupts globally enabled (I=0 in PRIMASK) Level: interrupt level must be less than BASEPRI Trigger: hardware action sets source-specific flag Interrupt remains pending if trigger is set but any other condition is not true Interrupt serviced once all conditions become true Need to acknowledge interrupt Clear trigger flag or will get endless interrupts! Bard, Gerstlauer, Valvano, Yerraballi

Interrupt Processing The execution of the main program is suspended
the current instruction is finished, suspend execution and push 8 registers (R0-R3, R12, LR, PC, PSR) on the stack LR set to 0xFFFFFFF9 (indicates interrupt return) IPSR set to interrupt number sets PC to ISR address The interrupt service routine (ISR) is executed clears the flag that requested the interrupt performs necessary operations communicates using global variables The main program is resumed when ISR executes BX LR pulls the 8 registers from the stack Bard, Gerstlauer, Valvano, Yerraballi

Registers R0-R3 parameters R4-R11 must be saved R14, R15 are important
SP (R13) refers to PSP or MSP We will use just the MSP PRIMASK has intr. enable (I) bit BASEPRI has allowed intr. priority Bard, Gerstlauer, Valvano, Yerraballi

Priority Mask Register
Disable interrupts (I=1) CPSID I Enable interrupts (I=0) CPSIE I MRS R0,PRIMASK CPSID I MRS PRIMASK,R0 Interface latency Bard, Gerstlauer, Valvano, Yerraballi

Program Status Register
Accessed separately or all at once Q = Saturation, T = Thumb bit Bard, Gerstlauer, Valvano, Yerraballi

Interrupt Program Status Register (ISPR)
Run debugger: - stop in ISR and - look at IPSR Bard, Gerstlauer, Valvano, Yerraballi

Interrupt Context Switch
Vector address for GPIO Port C Interrupt Number 18 corresponds to GPIO Port C Bard, Gerstlauer, Valvano, Yerraballi

Lecture 8: Periodic Timer Interrupts, Digital-to-Analog Conversion, Sound, Lab 6 Bard, Gerstlauer, Valvano, Yerraballi

Agenda Recap Agenda PLL Data structures FSMs, linked structure
Interrupts Agenda Periodic Interrupts Digital to Analog Conversion Nyquist Theorem Sound generation SysTick ISR Output one value to DAC Bard, Gerstlauer, Valvano, Yerraballi

77 total INTERRUPT VECTORS Bard, Gerstlauer, Valvano, Yerraballi Lab 7
Vector address Number IRQ ISR name in Startup.s NVIC Priority bits 0x 14 -2 PendSV_Handler NVIC_SYS_PRI3_R 23 – 21 0x C 15 -1 SysTick_Handler 31 – 29 0x 16 GPIOPortA_Handler NVIC_PRI0_R 7 – 5 0x 17 1 GPIOPortB_Handler 15 – 13 0x 18 2 GPIOPortC_Handler 0x C 19 3 GPIOPortD_Handler 0x 20 4 GPIOPortE_Handler NVIC_PRI1_R 0x 21 5 UART0_Handler 0x 22 6 UART1_Handler 0x C 23 7 SSI0_Handler 0x 24 8 I2C0_Handler NVIC_PRI2_R 0x 25 9 PWMFault_Handler 0x 26 10 PWM0_Handler 0x C 27 11 PWM1_Handler 0x 28 12 PWM2_Handler NVIC_PRI3_R 0x 29 13 Quadrature0_Handler 0x 30 ADC0_Handler 0x C 31 ADC1_Handler 0x 32 ADC2_Handler NVIC_PRI4_R 0x 33 ADC3_Handler 0x 34 WDT_Handler 0x C 35 Timer0A_Handler 0x 36 Timer0B_Handler NVIC_PRI5_R 0x 37 Timer1A_Handler 0x 38 Timer1B_Handler 0x C 39 Timer2A_Handler 0x000000A0 40 Timer2B_Handler NVIC_PRI6_R 0x000000A4 41 Comp0_Handler 0x000000A8 42 Comp1_Handler 0x000000AC 43 Comp2_Handler 0x000000B0 44 SysCtl_Handler NVIC_PRI7_R 0x000000B4 45 FlashCtl_Handler 0x000000B8 46 GPIOPortF_Handler 0x000000BC 47 GPIOPortG_Handler 0x000000C0 48 GPIOPortH_Handler NVIC_PRI8_R 0x000000C4 49 UART2_Handler 0x000000C8 50 SSI1_Handler 0x000000CC 51 Timer3A_Handler 0x000000D0 52 Timer3B_Handler NVIC_PRI9_R 0x000000D4 53 I2C1_Handler 0x000000D8 54 Quadrature1_Handler 0x000000DC 55 CAN0_Handler 0x000000E0 56 CAN1_Handler NVIC_PRI10_R 0x000000E4 57 CAN2_Handler 0x000000E8 58 Ethernet_Handler 0x000000EC 59 Hibernate_Handler 0x000000F0 60 USB0_Handler NVIC_PRI11_R 0x000000F4 61 PWM3_Handler 0x000000F8 62 uDMA_Handler 0x000000FC 63 uDMA_Error Lab 7 Lab 8 Lab 9 77 total INTERRUPT VECTORS Bard, Gerstlauer, Valvano, Yerraballi

Nested Vectored Interrupt Controller (NVIC)
Hardware unit that coordinates among interrupts from multiple sources Define priority level of each interrupt source (NVIC_PRIx_R registers) Separate enable flag for each interrupt source (NVIC_EN0_R and NVIC_EN1_R) Interrupt does not set I bit Higher priority interrupts can interrupt lower priority ones Bard, Gerstlauer, Valvano, Yerraballi

NVIC Registers High order three bits of each byte define priority
Address 31 – 29 23 – 21 15 – 13 7 – 5 Name 0xE000E400 GPIO Port D GPIO Port C GPIO Port B GPIO Port A NVIC_PRI0_R 0xE000E404 SSI0, Rx Tx UART1, Rx Tx UART0, Rx Tx GPIO Port E NVIC_PRI1_R 0xE000E408 PWM Gen 1 PWM Gen 0 PWM Fault I2C0 NVIC_PRI2_R 0xE000E40C ADC Seq 1 ADC Seq 0 Quad Encoder PWM Gen 2 NVIC_PRI3_R 0xE000E410 Timer 0A Watchdog ADC Seq 3 ADC Seq 2 NVIC_PRI4_R 0xE000E414 Timer 2A Timer 1B Timer 1A Timer 0B NVIC_PRI5_R 0xE000E418 Comp 2 Comp 1 Comp 0 Timer 2B NVIC_PRI6_R 0xE000E41C GPIO Port G GPIO Port F Flash Control System Control NVIC_PRI7_R 0xE000E420 Timer 3A SSI1, Rx Tx UART2, Rx Tx GPIO Port H NVIC_PRI8_R 0xE000E424 CAN0 Quad Encoder 1 I2C1 Timer 3B NVIC_PRI9_R 0xE000E428 Hibernate Ethernet CAN2 CAN1 NVIC_PRI10_R 0xE000E42C uDMA Error uDMA Soft Tfr PWM Gen 3 USB0 NVIC_PRI11_R 0xE000ED20 SysTick PendSV -- Debug NVIC_SYS_PRI3_R Bard, Gerstlauer, Valvano, Yerraballi

NVIC Interrupt Enable Registers
Two enable registers – NVIC_EN0_R and NVIC_EN1_R Each 32-bit register has a single enable bit for a particular device NVIC_EN0_R control the IRQ numbers 0 to 31 (interrupt numbers 16 – 47) NVIC_EN1_R control the IRQ numbers 32 to 47 (interrupt numbers 48 – 63) Bard, Gerstlauer, Valvano, Yerraballi

Interrupt Rituals Things you must do in every ritual
Initialize data structures (counters, pointers) Arm (specify a flag may interrupt) Configure NVIC Enable interrupt (NVIC_EN0_R) Set priority (e.g., NVIC_PRI1_R) Enable Interrupts Assembly code CPSIE I C code EnableInterrupts(); Bard, Gerstlauer, Valvano, Yerraballi

Interrupt Service Routine (ISR)
Things you must do in every interrupt service routine Acknowledge clear flag that requested the interrupt SysTick is exception; automatic acknowledge Maintain contents of R4-R11 (AAPCS) Communicate via shared global variables Bard, Gerstlauer, Valvano, Yerraballi

Interrupt Events Respond to infrequent but important events
Alarm conditions like low battery power Error conditions I/O synchronization Trigger interrupt when signal on a port changes Periodic interrupts Generated by the timer at a regular rate Systick timer can generate interrupt when it hits zero Reload value + frequency determine interrupt rate Bard, Gerstlauer, Valvano, Yerraballi

Synchronization Semaphore Mailbox – to be presented for Lab 8
Use global variable to communicate Semaphore One thread sets the flag The other treads waits for, and clears Mailbox – to be presented for Lab 8 FIFO queue – to be presented for Lab 9 Bard, Gerstlauer, Valvano, Yerraballi

Periodic Interrupts Data acquisition samples ADC
Lab 8 will sample at a fixed rate Signal generation output to DAC Audio player (we use the Systick interrupt to write samples out periodically in Lab 6) Communications Digital controller FSM Linear control system (EE362K) Demo PeriodicSystickInts starter C code Bard, Gerstlauer, Valvano, Yerraballi

Digital Representation of Analog Signals
Digitization: Amplitude and time quantization Bard, Gerstlauer, Valvano, Yerraballi

Conversion from Digital to Analog
Range 0 to 3.3V Resolution 3.3V/15 = 0.22V Precision 4 bits 16 alternative Speed Monotonic Bard, Gerstlauer, Valvano, Yerraballi

Digital ↔ Analog Conversion
Sampled at a fixed time, Dt Bard, Gerstlauer, Valvano, Yerraballi

Digital ↔ Analog Conversion
Digital in voltage and in time fs = 1/Dt Signal has frequencies 0 to ½ fs Bard, Gerstlauer, Valvano, Yerraballi

Digital-to-Analog Converter (DAC)
Binary Weighted DAC One resistor for each bit of output Resistor values in powers of 2 Resistance: R = V/I Two resistors R1 and R2 in series. Kirchhoff laws: V = V1 + V2, I = I1 = I2 Applied: V2 = R2 * I2 = R2 * I V = R1*I1 + R2*I2 = I*(R1+R2) Equivalent resistance: R = V / I = R1 + R2 Voltage divider: What is the voltage V2 at intermediate node? V2 = R2 * I = R2 / (R1+R2) * V Two resistors R1 and R2 in parallel: Kirchhoff laws: V = V1 = V2, I = I1 + I2 Applied: I = V1/R1 + V2/R2 = V * (1/R1 + 1/R2) Equivalent resistance: R = V / I = 1 / (1/R1 + 1/R2) 2-bit DAC on the right: A cascade of resistors R, 2R that can be switched to Vdd or ground. All resistors that are switched to Vdd (output bit Qx = 1) operate in parallel: Rdd = 1 / (Q1/R + Q0/2R) = 2R / (2Q1 + Q0) All resistors that are switched to ground operate in parallel: R’ = 1 / (Q’1/R + Q’0/ 2R) = 2R / (2Q’1 + Q’0) Total resistance of Vdd and ground resistor networks in series: 2R * ((2Q’1 + Q’0) + (2Q1 + Q0)) R * (2 + 1) R = Rdd + R’ = = (2Q1 + Q0) * (2Q’1 + Q’0) (2Q1 + Q0) * (2Q’1 + Q’0) Voltage divider: Vout = Vdd * R’ / R = Vdd * (2Q1 + Q0) / 3 Bard, Gerstlauer, Valvano, Yerraballi

3 bit DAC Bard, Gerstlauer, Valvano, Yerraballi R2 10 kohm R1 20 R0 40
PB2 PB1 PB0 kohm equation Vout (V) 0.000 1 3.3 R2||R1 6.67 3.3*(R1||R2)/(R0+R1||R2) 0.471 2 R2||R0 8.00 3.3*(R2||R0)/(R1+R2||R0) 0.943 3 R1||R0 13.33 3.3*R2/(R2+R1||R0) 1.414 4 3.3*(R1||R0)/(R2+R1||R0) 1.886 5 3.3*R1/(R1+R2||R0) 2.357 6 3.3*R0/(R0+R2||R1) 2.829 7 3.300 Bard, Gerstlauer, Valvano, Yerraballi

Other Types of DACs Binary weighted cascading ladder
R-2R Ladder DAC Binary weighted cascading ladder Improved precision owing to ability to select resistors of equal value Bard, Gerstlauer, Valvano, Yerraballi

DAC Performance Resolution, range, precision
Maximum sampling frequency Monotonicity Input increase causes output increase (always) Bard, Gerstlauer, Valvano, Yerraballi

Resistor Network for 4-bit DAC
Vout = Vdd * (8*Q3 + 4*Q2 + 2*Q1 + Q0)/15 Bard, Gerstlauer, Valvano, Yerraballi

Dynamic testing Bard, Gerstlauer, Valvano, Yerraballi

Sound Loudness and pitch Controlled by amplitude and frequency
Humans can hear from about 25 to 20,000 Hz. Middle A is 440 Hz Other notes on a keyboard are determined 440 * 2N/12, where N is no. of notes from middle A. Middle C is Hz. Music contains multiple harmonics Bard, Gerstlauer, Valvano, Yerraballi

Tempo Tempo defines note duration Quarter note = 1 beat
120 beats/min => ½ s duration Bard, Gerstlauer, Valvano, Yerraballi

Chord Two notes at the same time Superimposed waveforms
262 Hz (low C) and a 392 Hz (G) Bard, Gerstlauer, Valvano, Yerraballi

Instrument Characteristics
Waveform shape of a trumpet sound Plucked string signal with envelope Bard, Gerstlauer, Valvano, Yerraballi

Synthesizing Digital Music
Nyquist’s Sampling Theorem We can reproduce any bandlimited signal from its samples if we sample correctly and at a frequency, fs, that is at least twice the highest frequency component of the signal, fmax. Where do we get the samples? We could sample a series of musical tones We can compute the samples Bard, Gerstlauer, Valvano, Yerraballi

Synthesizing Digital Music (cont.)
What is a musical tone? A sinusoid of a particular frequency Notes vary by twelfth root of 2 ~ 1.059 What would the samples be? Fixed point numbers How do we generate a sinusoid? Output appropriate digital values via a resistor network that effectively produces an pseudo-analog signal What about frequency? Employ a programmable timer to tell us when to output the next value Bard, Gerstlauer, Valvano, Yerraballi

Synthesizing Digital Music (cont.)
440 Hz sine wave generated by 6-bit DAC Frequency spectrum Bard, Gerstlauer, Valvano, Yerraballi

Music Generation – Lab 6 Objectives
Employ LM4F/TM4C to generate appropriately scaled digital outputs at a specified frequency Three frequencies are required Frequencies are to be determined by switch settings Four digital outputs are inputs to a resistor network that serves as a digital-to-analog converter (DAC) Four output bits => 16 levels Bard, Gerstlauer, Valvano, Yerraballi

Music Generation (cont.)
DAC hardware Employ least significant four bits of a GPIO port Arrange resistor network in 1, 2, 4, 8 sequence Each port bit can assume digital levels of 0 and 3.3 V Ports are current limited – max 8 mA R3 R2 R1 R0 Bard, Gerstlauer, Valvano, Yerraballi

DAC software Interactions via device drivers Two device driver functions required void DAC_Init(void); // initializes the device void DAC_Out(unsigned char data); // transfers data to device (Device driver provides the functions associated with the device but hides the detailed actions necessary to implement the functions.) Bard, Gerstlauer, Valvano, Yerraballi

Interpretation of data Note has three parameters Amplitude (loudness) Frequency (pitch) Duration Amplitude is a digitally approximated sinusoid Sinusoid varies between 0 and 3.3 volts Frequency is selected by switches Four states – stop, note_1, note_2, and note_3 Duration is period switch(es) activated Bard, Gerstlauer, Valvano, Yerraballi

4-bit Sinusoid Table 32 value sinusoid
SinTab 8,9,11,12,13,14,14,15,15,15,14 14,13,12,11,9,8,7,5,4,3,2 2,1,1,1,2,2,3,4,5,7 32 value sinusoid Bard, Gerstlauer, Valvano, Yerraballi

Musical Notes Bard, Gerstlauer, Valvano, Yerraballi

Tone Generation For a 440Hz tone unsigned long I;
// 4-bit 32-element sine wave const unsigned char wave[32]= { 8,9,11,12,13,14,14,15,15,15,14 14,13,12,11,9,8,7,5,4,3,2 2,1,1,1,2,2,3,4,5,7}; For a 440Hz tone Assume a bus clock frequency of 50 MHz SysTick count every 20ns Each cycle of the 440 Hz sinusoid requires: (50*106 counts/s)/440 Hz = SysTick counts Each cycle consists of 32 values each of duration: interrupt counts/32 values = SysTick counts/value DAC values change every us SysTick ISR Output one value to DAC Bard, Gerstlauer, Valvano, Yerraballi

Lab 6 ISR Each Systick interrupt In main program
Output one value from the array to DAC Increment index to array (wrap back to zero) In main program If a switch is pressed set SysTick period (arm) If no switches are pressed then disarm SysTick ISR Output one value to DAC Bard, Gerstlauer, Valvano, Yerraballi

Other Instruments // 6-bit 64-element bassoon wave
const unsigned char Bassoon[64] = { 33,37,37,36,35,34,34,33,31,30,29, 30,33,43,58,63,52,31,13,4,5,10,16, 23,32,40,46,48,44,38,30,23,17,12,11, 15,23,32,40,42,39,32,26,23,23,24,25, 25,26,29,30,31,32,34,37,39,37,35,34, 34,34,33,31,30}; // 6-bit 64-element guitar wave const unsigned char Guitar[64] = { 20,20,20,19,16,12,8,4,3,5,10,17, 26,33,38,41,42,40,36,29,21,13,9, 9,14,23,34,45,52,54,51,45,38,31, 26,23,21,20,20,20,22,25,27,29, 30,29,27,22,18,13,11,10,11,13,13, 13,13,13,14,16,18,20,20,20}; Bard, Gerstlauer, Valvano, Yerraballi

Lecture 9: Local Variables, Stack Frames, Recursion, Fixed-Point Numbers, LCD Bard, Gerstlauer, Valvano, Yerraballi

Agenda Recap Agenda Interrupts DAC, Sound Local Variables Stack frames
Recursion Fixed-point numbers LCD Interfacing Bard, Gerstlauer, Valvano, Yerraballi

Local Variables Scope => from where can it be accessed
local means restricted to current program segment global means any software can access it Allocation/Lifetime => when is it created & destroyed dynamic allocation using registers or stack permanent allocation assigned a block of memory Bard, Gerstlauer, Valvano, Yerraballi

Local Variables temporary information used only by one software module
Local variables => local scope, dynamic allocation temporary information used only by one software module allocated, used, then deallocated not permanent implement using the stack or registers R0-R3 and R12 temporary data R4-R11 more permanent data Bard, Gerstlauer, Valvano, Yerraballi

In C Local variables Global Variables
Public: local scope, dynamic allocation void MyFunction(void){ short myLocalVariable; } Private: local scope, permanent allocation void MyFunction(void){ static short count; count++; } Global Variables Public: global scope, permanent allocation // accessible by all modules short myGlobalVariable; void MyFunction(void){…} Private: global scope(only to the file), permanent allocation //accessible in this file only static short myPrivateGlobalVariable; // callable by other // routines in this file only void static MyPrivateFunction(void){…} Bard, Gerstlauer, Valvano, Yerraballi

Why use Stack for Locals?
Dynamic allocation/release allows for reuse of memory Limited scope of access provides for data protection Only the program that created the local can access it The code is reentrant. The code is relocatable The number of variables is more than available registers Bard, Gerstlauer, Valvano, Yerraballi

Recall Stack Rules Program segments should have an equal number of pushes and pulls Push with multiple registers will always put the lower numbered register’s contents in the lower address. Pop with multiple registers will always get the lower numbered register’s contents from the lower address. Push SP=SP-4 Store 32 bits at SP Pop Read 32 bits at SP SP=SP+4 Bard, Gerstlauer, Valvano, Yerraballi

Stack frame using SP ; *****binding phase*************** sum EQU 0 ;32-bit unsigned number n EQU 4 ;32-bit unsigned number ; 1)*****allocation phase ********* calc PUSH {R4,LR} SUB SP,#8 ;allocate n,sum ; 2)******access phase ************ MOV R0,#0 STR R0,[SP,#sum] ;sum=0 MOV R1,#1000 STR R1,[SP,#n] ;n=1000 loop LDR R1,[SP,#n] ;R1=n LDR R0,[SP,#sum] ;R0=sum ADD R0,R ;R0=sum+n STR R0,[SP,sum] ;sum=sum+n LDR R1,[SP,#n] ;R1=n SUBS R1,# ;n-1 STR R1,[SP,#n] ;n=n-1 BNE loop ; 3)******deallocation phase ***** ADD SP,#8 ;deallocation POP {R4,PC} ;R0=sum unsigned long calc(void) { unsigned long sum, n; sum = 0; for(n=1000; n>0; n--) { sum=sum+n; } return sum; Program 7.3. Stack pointer implementation of a function with two local 32-bit variables. Bard, Gerstlauer, Valvano, Yerraballi

Stack frame using R11 ; *****binding phase*************** sum EQU 0 ;32-bit unsigned number n EQU 4 ;32-bit unsigned number ; 1)*****allocation phase ********* calc PUSH {R4,R11,LR} SUB SP,#8 ;allocate n,sum MOV R11,SP ;frame pointer ; 2)******access phase ************ MOV R0,#0 STR R0,[R11,#sum] ;sum=0 MOV R1,#1000 STR R1,[R11,#n] ;n=1000 loop LDR R1,[R11,#n] ;R1=n LDR R0,[R11,#sum] ;R0=sum ADD R0,R ;R0=sum+n STR R0,[R11,sum] ;sum=sum+n LDR R1,[R11,#n] ;R1=n SUB R1,# ;n-1 STR R1,[R11,#n] ;n=n-1 BNE loop ; 3)******deallocation phase ***** ADD SP,#8 ;deallocation POP {R4,R11,PC} ;R0=sum unsigned long calc(void) { unsigned long sum,n; sum = 0; for(n=1000; n>0; n--) { sum=sum+n; } return sum; Program 7.4. Stack frame pointer implementation of a function with two local 32-bit variables. Bard, Gerstlauer, Valvano, Yerraballi

Push parameters on stack
; Inputs R0 is x ; R1 is y ; R2 is z ; Output R0 is return value sum EQU 0 ;32-bit signed number x EQU 4 ;32-bit signed number y EQU 8 ;32-bit signed number z EQU 12 ;32-bit signed number Add3 PUSH {R0,R1,R2,LR} SUB SP,#4 ;allocate sum ; body of the function LDR R0,[SP,#x] ADD R0,R0,[SP,#y] ADD R0,R0,[SP,#z] STR R0,[SP,#sum] ADD SP,#16 ;deallocate POP {PC} long Add3(long x, long y, long z) { long sum; sum = x+y+z; return sum; } Pushing parameters on stack makes them similar to local variables Bard, Gerstlauer, Valvano, Yerraballi

Recursion using the stack
; Input R0 is n ; Output R0 is return value n EQU 0 ;input parameter Fact PUSH {R0,LR} CMP R0,#1 BLS base SUB R0,#1 ;n-1 BL Fact ;Fact(n-1) LDR R1,[SP,#n] MUL R0,R0,R1 ;n*Fact(n-1) B done base MOV R0,#1 done ADD SP,#4 ;deallocate POP {PC} unsigned long Fact(unsigned long n) { if(n<=1) return 1; return n*fact(n-1); } Recursion requires putting parameters and locals on the stack Bard, Gerstlauer, Valvano, Yerraballi

Fixed-Point Numbers How? (value = I*)
I (Variable Integer) is a 16-bit unsigned integer. It is stored and manipulated in memory.  (Fixed Constant) that represents the resolution. It is not stored but is usually written in comments ; implicit. (What about negative numbers?) Why? (wish to represent non-integer values) Next lab measures distance from 0 to 3 cm E.g., cm When? (range is known, range is small) Range is 0 to 3cm Resolution is cm Bard, Gerstlauer, Valvano, Yerraballi

Fixed-Point Numbers: Decimal
Decimal Fixed-Point (Value = I*10m) I is a 16-bit unsigned integer (variable integer)  = 10m decimal fixed-point (fixed constant) For example with m=-3 (resolution of or milli) the value range is to What is  represented as, in Decimal Fixed-Point?  ( …) = I* => I = Integral approximation of ( …*103) I = Integral approximation of ( ) I = 3142 Decimal Fixed-Point numbers are human-friendly -easy to input/output to humans Bard, Gerstlauer, Valvano, Yerraballi

Fixed-Point Numbers: Binary
Binary Fixed-Point (Value = I*2m) I is a 16-bit unsigned integer (variable integer)  = 2m binary fixed-point (fixed constant) For example with m=-8 (resolution of 1/256) What is  represented as, in binary Fixed Point?  ( …)= I*2-8 => I = Integral approximation of( …*28) I = Integral approximation of( ) I = 804 Binary Fixed-Point numbers are computer-friendly -runs very fast because shifting is fast Bard, Gerstlauer, Valvano, Yerraballi

Output Output an integer. Assume integer, n, is between 0 and 9999.
OutChar(0x30+n/1000) ;thousand’s digit n = n%1000 OutChar(0x30+n/100) ;hundred’s digit n = n%100 OutChar(0x30+n/10) ;ten’s digit OutChar (0x30+n%10) ;one’s digit Output a fixed-point decimal number. Assume the integer part of the fixed point number, n, is between 0 and 9999, and resolution is OutChar(0x30+n/1000) ;thousand’s digit n = n%1000 OutChar(0x2E) ;decimal point OutChar(0x30+n/100) ;hundred’s digit n = n%100 OutChar(0x30+n/10) ;ten’s digit OutChar (0x30+n%10) ;one’s digit Bard, Gerstlauer, Valvano, Yerraballi

Input/Output Synchronization
Processor-Peripheral Timing Mismatch Peripherals, e.g., displays, sensors, switches, generally operate MUCH slower than processor instruction times Processor ~ MHz Peripheral ~ kHz or Hz MANY instructions can be executed while peripheral processes information Bard, Gerstlauer, Valvano, Yerraballi

Input/Output Sync. (cont.)
Peripheral primitive states READY Peripheral is ready to initiate an I/O transfer NOT READY Peripheral is unable to perform I/O transfer BUSY READY peripheral becomes BUSY when I/O transfer initiated Peripheral remains BUSY for duration of I/O transfer Another transfer can NOT be initiated NOT BUSY READY peripheral is able to initiate another I/O operation Bard, Gerstlauer, Valvano, Yerraballi

Input/Output Sync. (cont.)

I/O Sync Options (1) What to do while the peripheral is BUSY?
BLIND CYCLE TRANSFER Suppose that a BUSY control signal is not available Perform I/O operation Wait for a period of time that is guaranteed to be sufficient for operation to complete Initiate next operation Bard, Gerstlauer, Valvano, Yerraballi

BUSY-WAIT (e.g., ready-busy, test- transfer) Poll peripheral status – wait for READY/NOT BUSY Perform other tasks between polls Unless timed correctly, under/over run possible One solution: POLL CONTINUOUSLY Bard, Gerstlauer, Valvano, Yerraballi

INTERRUPT/TRANSFER Hardware INTERRUPTS processor on condition of READY/NOT BUSY Facilitates performing other – background - processing between I/O transfers Processor changes context when current transfer complete Requires program structure to process context change Bard, Gerstlauer, Valvano, Yerraballi

DIRECT MEMORY ACCESS TRANSFER Special purpose hardware logic monitors status of BUSY signal and maintains addresses of data to be communicated Requires address and block size initialization On the condition of NOT BUSY logic communicates next data element and increments address When transfer is complete, logic provides COMPLETE INTERRUPT Our LM4F120/TM4C123 supports DMA (but EE319K doesn’t use it) Bard, Gerstlauer, Valvano, Yerraballi

Latency Software latency or interface latency
Time from when new input is ready until time software reads data. Time from when output is idle until time software writes new data. Execute tasks at periodic intervals, latency is delay from when it should run until it does run Interrupts guarantee an upper bound on the software response time Count maximum time running with I=1, plus Time to process the interrupt. Bard, Gerstlauer, Valvano, Yerraballi

Real-Time System Real-time system Throughput/bandwidth Priority
a system that can guarantee a worst case latency Throughput/bandwidth maximum data flow (bytes/s) that can be processed by the system Priority determines the order of service among two or more requests Bard, Gerstlauer, Valvano, Yerraballi

Kentec EB-LM4F120-L35 A 3.5 inch QVGA TFT LCD module
Connects to the LaunchPad as a booster pack Quarter VGA: WxD of 320x240 pixels Color display with 16-bits per pixel Is a capacitive touchscreen – we will not use the touchscreen in EE319K Device driver library SSD2119.c provided to you Each partnership checks one out of the second floor, but it will cost you over $100 if you loose it Bard, Gerstlauer, Valvano, Yerraballi

LCD – Operation Simplified Interface to Kentec EB- LM4F120-L35
Data Bus (PB0-7) Control Bus (PA4-7) Bard, Gerstlauer, Valvano, Yerraballi

Interface signals Data bus Control bus
PB0-7 hold the 8-bit command or Data to be sent We will use 8-bit commands and 16-bit data. Send 16-bit data as two consecutive 8-bit writes on the bus 8-bit command means MSbyte is zero Control bus PA7(CS) : Chip Select PA6(RS): Command/Data Select PA5(WR): Write control signal for LCD PA4(RD): Read control signal for LCD PA3,2 and PE4,5 used for touchscreen PF2 controls backlight Bard, Gerstlauer, Valvano, Yerraballi

LCD Programming LCD_WriteCommand: Involves 7 steps performed to send 8-bit Commands to the LCD RD is high throughout CS is low during communication RS is low during command write Microcontroller must do these steps All control signals are high before and after the command write Bard, Gerstlauer, Valvano, Yerraballi

LCD Programming LCD_WriteData: Involves 7 steps performed to send 16-bit data to the LCD RD is high throughout CS is low during communication RS is high during data write Microcontroller must do these steps All control signals are high before and after the data write Bard, Gerstlauer, Valvano, Yerraballi

LCD – Lab7 Lab assignment (Lab7Starter.zip) Interface LCD to TI board
Develop device driver to serve as interface between TM4C123 and Kentec display Use main program (in lab7.s) that employs device driver in Lcd.s Bard, Gerstlauer, Valvano, Yerraballi

Lab7 – Your responsibility
IO.s – Switch and Heartbeat module IO_Init IO_HeartBeat IO_Touch Lcd.s – LCD Device driver module LCD_WriteData LCD_WriteCommand Wait10ms Print.s – Print module LCD_OutFix LCD_OutDec Do not use SysTick for this wait, because we will add SysTick interrupts in Labs 8, 9, 10. Bard, Gerstlauer, Valvano, Yerraballi

Summary Stack is useful for local variables, parameter passing
Draw stack picture by hand executing assembly code Fixed-point allows non-integers without FP hardware LCD is an output device for embedded systems Text, graphics, touch pads, color Bard, Gerstlauer, Valvano, Yerraballi

Lecture 10: Sampling, Analog-to-Digital Conversion Bard, Gerstlauer, Valvano, Yerraballi

Agenda Recap Outline Local Variables Stack frames Recursion
Fixed-point numbers LCD device driver (Lab 7) Outline Sampling, Nyquist theorem Analog to Digital Conversion Bard, Gerstlauer, Valvano, Yerraballi

Analog to Digital Converter (ADC)

Nyquist Theorem A bandlimited analog signal that has been sampled can be perfectly reconstructed from an infinite sequence of samples if the sampling rate fs exceeds 2fmax samples per second, where fmax is the highest frequency in the original signal. If the analog signal does contain frequency components larger than (1/2)fs, then there will be an aliasing error. Aliasing is when the digital signal appears to have a different frequency than the original analog signal. Valvano Postulate: If fmax is the largest frequency component of the analog signal, then you must sample more than ten times fmax in order for the reconstructed digital samples to look like the original signal when plotted on a voltage versus time graph. Bard, Gerstlauer, Valvano, Yerraballi

Sampling (option 1) 200Hz signal sampled at 2000Hz

Sampling (option 1) 2200Hz signal sampled at 2000Hz This is aliasing

Sampling (option 2) A signal with DC, 100Hz and 400Hz sampled at 1600Hz Bard, Gerstlauer, Valvano, Yerraballi

Sampling (option 2) 1500Hz signal sampled at 1600Hz This is aliasing

Analog to Digital Converter (ADC)
Successive approximation ADC VIN is approximated as a static value in a sample and hold (S/H) circuit the successive approximation register (SAR) is a counter that increments each clock as long as it is enabled by the comparator the output of the SAR is fed to a DAC that generates a voltage for comparison with VIN when the output of the DAC = VIN the value of SAR is the digital representation of VIN end of conversion Bard, Gerstlauer, Valvano, Yerraballi

Sample-And-Hold Circuit
S/H Analog Input (AI) is sampled when the switch is closed and its value is held on the capacitor where it becomes the Analog Output (AO) Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 Sampling Range/Resolution 3V internal reference voltage
0x000 at 0 V input 0xFFF at 3 V resolution = range/precision = 3V/4096 alternatives < 1mV Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 PE2=Ain1 used for Lab 8, 9, 10
Twelve analog input channels Single-ended and differential-input configurations On-chip internal temperature sensor Sample rate up to one million samples/second Hz Flexible, configurable analog-to-digital conversion Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs Flexible trigger control Controller (software) We will use software initiated trigger Timers Analog Comparators PWM GPIO Hardware averaging of up to 64 samples for improved accuracy Converter uses an internal 3V reference Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 PE2=Ain1 used for Lab 8, 9, 10 Ain1PE2
Software initiated Use sequencer 3 Bit 3 is done flag Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 PD4=Ain4 used for DLL testing
PE2=Ain1 used for Lab 8, 9, 10 PE4=Ain9 used in book and ADCSWTrigger_4F120.zip Twelve different pins can be used to sample analog inputs. Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 TM4C ADC registers

ADC on TM4C123 TM4C123 ADC Operation select rate select sequencer
select trigger select channel select sample mode 0 not temperature 1 set completion flag 1 end sequence 0 not differential MAXADCSPD bits in SYSCTL_RCGC0_R EM3, EM2, EM1, and EM0 bits in ADC_EMUX_R ADC0_SSCTL3_R = 0x06; Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 Initialization
Enable ADC clock: set bit 16 in SYSCTL_RCGC0_R Set 125kHz ADC conversion speed: clear bits 8,9 in SYSCTL_RCGC0_R Set sequencer priority: 0,1,2,3 in ADC0_SSPRI_R Disable selected sequence 3: zero bit 3 of ADC0_ACTSS_R Set software start trigger event: zero bits of ADC0_EMUX_R Set input source (0-11): write channel number in bits 3-0 of ADC0_SSMUX3_R (channel 9 is PE4, channel 1 is PE2) Set sample control bits: write 0110 in bits 3-0 ADC0_SSCTL3_R to disable temp measurement, notify on sample complete, indicate single sample in sequence, and denote single-ended signal mode Disable interrupts: zero bit 3 of ADC0_IM_R Enable selected sequencer 3: set bit 3 of ADC0_ACTSS_R Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 Channel 9 is PE4 void ADC0_InitSWTriggerSeq3_Ch9(void){ volatile unsigned long delay; SYSCTL_RCGC2_R |= 0x ; // 1) activate clock for Port E delay = SYSCTL_RCGC2_R; // allow time to stabilize GPIO_PORTE_DIR_R &= ~0x10; // 2) make PE4 input GPIO_PORTE_AFSEL_R |= 0x10; // 3) enable alt funct on PE4 GPIO_PORTE_DEN_R &= ~0x10; // 4) disable digital I/O on PE4 GPIO_PORTE_AMSEL_R |= 0x10; // 5) enable analog funct on PE4 SYSCTL_RCGC0_R |= 0x ; // 6) activate ADC0 delay = SYSCTL_RCGC2_R; SYSCTL_RCGC0_R &= ~0x ; // 7) 125kHz ADC conversion speed ADC0_SSPRI_R = 0x0123; // 8) Seq 3 is highest priority ADC0_ACTSS_R &= ~0x0008; // 9) disable sample sequencer 3 ADC0_EMUX_R &= ~0xF000; // 10) seq3 is software trigger ADC0_SSMUX3_R = (ADC0_SSMUX3_R&0xFFFFFFF0)+9; // 11) Ain9 (PE4) ADC0_SSCTL3_R = 0x0006; // 12) no TS0 D0, yes IE0 END0 ADC0_ACTSS_R |= 0x0008; // 13) enable sample sequencer 3 } Book shows Ain9=PE Lab 8, 9, 10 use Ain1=PE2 Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 Analog to digital conversion Set software trigger
Write to PSSI bit 3 Busy-Wait Raw Interrupt Status = RIS bit 3 Poll until sample complete Read sample Read from SSFIFO3 Clear sample complete flag Write to ISC bit 3 Bard, Gerstlauer, Valvano, Yerraballi

ADC on TM4C123 //------------ADC_InSeq3------------
// Busy-wait analog to digital conversion // Input: none // Output: 12-bit result of ADC conversion unsigned long ADC0_InSeq3(void){ unsigned long data; ADC0_PSSI_R = 0x0008; while((ADC0_RIS_R&0x08)==0){}; result = ADC0_SSFIFO3_R&0xFFF; ADC0_ISC_R = 0x0008; return data; } Bard, Gerstlauer, Valvano, Yerraballi

Lecture 11: Data Acquisition, Numerical Fixed-Point Calculations, Lab 8 Bard, Gerstlauer, Valvano, Yerraballi

Agenda Recap Agenda Sampling, Nyquist Analog to Digital Conversion
Exam 2 Pointers, Array and String Manipulation, FSMs Data acquisition Numerical fixed-point calculations Lab 8 Bard, Gerstlauer, Valvano, Yerraballi

Exam 2 review 0) Being able to quickly design, implement, and debug assembly software 1) Understanding differences between data and address, being able to use pointers and indices 2) Understanding differences between 8-bit, 16- bit data and 32-bit data 3) Understanding differences between signed and unsigned integers 4) Programming if-then if-then-else for-loops while-loops and do-while-loops in assembly 5) Processing a variable-length array or string, either size first or terminating code at end 6) Addition subtraction multiplication and division

Exam 2 review 7) Shift left and right (signed and unsigned)
8) Call by value, call by reference, return by value 9) AAPCS Program conventions Save and restore R4-R11,LR if you wish to modify Parameter passing in registers R0,R1,R2,R3 All input parameters promoted to 32 bits Return parameter in R0 10) Implementation of FSM using a linked data structure or using a table structure with an index Mealy and Moore Not a real port, so no bit-specific addressing Read modify write sequences to be friendly (including input pin) 11) Accessing arrays and strings using pointers and indices Stepping through two or more arrays at a time 8/16/32-bit data, signed/unsigned numbers

Exam 2 review A) You may be given one or more variable length arrays of data, buf[i] The size may be the first entry There may be a termination code The data may be 8-bit ASCII characters or integers The integers may be 8 16 or 32 bits Integers may be signed or unsigned A pointer to this array may be passed in R0 You may be asked to deal with special cases: size=0, size too big, overflow

Exam 2 Array problems Determine the size of the array
Return the first element of the array Find the maximum or minimum element in an array Find the sum of all the elements Find the average of all the elements Find the mode of all the elements Find the range = maximum - minimum Find the maximum or minimum slope (buf[i+1]-buf[i]) Find the maximum or minimum absolute value Count the number of times a particular value occurs (buf[i]==1000) Search for the occurrence of one string in another Concatenate two strings together Delete characters from a string Insert one string into another Move data from one place to another within an array or string Sort the array (we will give the steps)

Exam 2 FSM problems Convert a FSM graph to a linked data structure or table with an index Write a Mealy FSM controller (with or without timer wait) Write a Moore FSM controller (with or without timer wait) It also may involve accessing a linked structure like Lab 5

Exam 2 Runs on your laptop Written in assembly (no C)
Keil in simulation (no board) During exam: Keil, Keil help, PC calculator Needs internet to download and upload Battery power Written in assembly (no C) No SysTick, no interrupts Overall grade a combination of Numerical score from grader Program style (reviewed later) Tricking the grader is considered bad

Data Acquisition System (Lab 8)
Hardware Transducer Electronics ADC Software ADC device driver Timer routines Output compare interrupts LCD driver Measurement system How fast to update Fixed-point number system Algorithm to convert ADC into position Bard, Gerstlauer, Valvano, Yerraballi

Analog Input Device Transducer – A device actuated by power from one system that supplies power in the same or other form to another system. Bard, Gerstlauer, Valvano, Yerraballi

Transducer Circuit Position to voltage

Data Acquisition System
Data flow graph Bard, Gerstlauer, Valvano, Yerraballi

Data Acquisition System
Call graph Bard, Gerstlauer, Valvano, Yerraballi

Thread Synchronization in Lab 8
Background thread Foreground thread SysTick ISR Sample ADC Store in ADCmail Set ADCstatus Main loop Wait for ADCstatus Read ADCmail Clear ADCstatus Convert to distance Display on LCD Bard, Gerstlauer, Valvano, Yerraballi

Sampling Jitter Definition of time-jitter, δt:
Let nΔt be the time a task is scheduled to be run and tn the time the task is actually run Then δtn= tn – nΔt Real time systems with periodic tasks, must have an upper bound, k, on the time-jitter -k ≤ δtn ≤ +k for all n Bard, Gerstlauer, Valvano, Yerraballi

Measurement Resolution: Limiting factors Accuracy: Limiting factors
Transducer noise Electrical noise ADC precision Software errors Accuracy: Limiting factors Resolution Calibration Transducer stability Average accuracy (with units of x) = Bard, Gerstlauer, Valvano, Yerraballi

Fixed-Point Revisited
Why: express non-integer values no floating point hardware support (want it to run fast) When: range of values is known range of values is small How: 1) variable integer, called I. may be signed or unsigned may be 8, 16 or 32 bits (precision) 2) fixed constant, called  (resolution) value is fixed, and can not be changed not stored in memory specify this fixed content using comments value  integer •  Bard, Gerstlauer, Valvano, Yerraballi

Fixed-Point Numbers The value of the fixed-point number:
Fixed-point number  I• Smallest value = Imin • D, where Imin is the smallest integer Largest value = Imax • D, where Imax is the largest integer Decimal fixed-point, =10m Decimal fixed-point number = I • 10m Nice for human input/output Binary fixed-point, =2m Binary fixed-point number = I • 2m Easier for computers to perform calculations Bard, Gerstlauer, Valvano, Yerraballi

Fixed-Point Math Example
Consider the following calculation. C = 2**R The variables C, and R are integers 2p ≈ 6.283 C = (6283*R)/1000 Bard, Gerstlauer, Valvano, Yerraballi

Fixed-Point Math Example
Calculate the volume of a cylinder V = *R2 * L The variables are fixed-point R = I*2-4 cm L = J*2-4 cm V = K*2-8 cm3 2p ≈ 201*2-5 K = (201*I*I*J)>>9 Bard, Gerstlauer, Valvano, Yerraballi

Make a Voltmeter with ADC
Vin (V) Analog in N Digital out I (1 mV) Variable part LCD 0.000 0.75 1024 750 0.750 1.5 2048 1500 1.500 2.25 3072 2250 2.250 3 4096 3000 3.000 =0.001 V Vin = 3•N/4096 how ADC works Vin = I • definition of fixed point I = (3000*N)/ substitution I = (m•N+b)/ calibrate to get m and b Bard, Gerstlauer, Valvano, Yerraballi

Lab 8 Calibration Bard, Gerstlauer, Valvano, Yerraballi

Lecture 12: Serial Communication (UART), Lab 9, FIFO Queues Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Agenda Recap Agenda ADC, fixed-point Assembly-C mix Lab 8
Communication Serial: UART, interrupts FIFO Queues used as buffers in communication Lab 9: Distributing Lab 8 Transmitter uses ADC to read potentiometer Receiver uses LCD to display position. FIFO serves as buffer at receiver Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Universal Asynchronous Receiver/Transmitter (UART)
UART (Serial Port) Interface Send/receive a frame of (5-8) data bits with a single (start) bit prefix and a 1 or 2 (stop) bit suffix Baud rate is total number of bits per unit time Baudrate = 1 / bit-time Bandwidth is data per unit time Bandwidth = (data-bits / frame-bits) * baudrate Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

TM4C123 LaunchPad I/O Pins

RS-232 Serial Port // this U1Tx PD3 not connected // this U1Rx PD2 tied to U1Tx PD3 of other microcontroller Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Serial I/O Serial communication
Transmit Data (TxD), Receive Data (RxD), and Signal Ground (SG) implement duplex communication link Both communicating devices must operate at the same bit rate Least significant bit sent first Full duplex Half duplex Simplex Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

UART - Transmitter Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

UART - Transmitter Tx Operation Data written to UART0_DR_R
passes through 16-element FIFO permits small amount of data rate matching between processor and UART Shift clock is generated from 16x clock permits differences in Tx and Rx clocks to be reconciled Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

UART - Receiver Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

UART - Receiver Rx Operation RXFE is 0 when data are available
RXFF is 1 when FIFO is full FIFO entries have four control bits BE set when Tx signal held low for more than one frame (break) OE set when FIFO is full and new frame has arrived PE set if frame parity error FE set if stop bit timing error Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

UART – Overrun Error 17 frames transmitted and none read
Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

TM4C UART0 – Registers Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

TM4C UART Setup UART0 operation
UART clock started in RCGC1 and digital port clock started in RCGC2 UART0_CTL_R contains UART enable (UARTEN), Tx (TXE), and Rx enable (RXE) set each to 1 to enable UART disabled during initialization UART0_IBRD_R and UART_FBRD_R specify baud rate bit rate = (bus clock frequency)/(16*divider) ex: want 19.2 kb/s and bus clock is 8 MHz 8 MHz/(16*19.2 k) = = Tx and Rx clo ck rates must be within 5% to avoid errors GPIO_PORTA_AFSEL_R to choose alternate function Write appropriate values to GPIO_PORTA_PCTL_R (See table on slide 4) GPIO_PORTA_DEN_R Enable digital I/O on pins 1-0 GPIO_PORTA_AMSEL_R no Analog I/O on pins 1-0 write to UART0_LCRH_R to activate Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

UART Setup // Assumes a 50 MHz bus clock, creates 115200 baud rate
void UART_Init(void){ SYSCTL_RCGC1_R |= 0x0001; // activate UART0 SYSCTL_RCGC2_R |= 0x0001; // activate port A UART0_CTL_R &= ~0x0001; // disable UART UART0_IBRD_R = 27; // IBRD=int( /(16*115,200)) = int( ) UART0_FBRD_R = 8; // FBRD = round( * 64) = 8 UART0_LCRH_R = 0x0070; // 8-bit length, enable FIFO UART0_CTL_R = 0x0301; // enable RXE, TXE and UART GPIO_PORTA_AFSEL_R |= 0x03; // alt funct on PA1-0 GPIO_PORTA_PCTL_R = (GPIO_PORTA_PCTL_R&0xFFFFFF00)+0x ; GPIO_PORTA_DEN_R |= 0x03; // digital I/O on PA1-0 GPIO_PORTA_AMSEL_R &= ~0x03; // No analog on PA1-0 } Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

UART Synchronization Busy-wait operation

UART Busy-Wait Send/Recv
// Wait for new input, // then return ASCII code unsigned char UART_InChar(void) { while((UART0_FR_R&0x0010) != 0); // wait until RXFE is 0 return((unsigned char)(UART0_DR_R&0xFF)); } // Wait for buffer to be not full, // then output void UART_OutChar(unsigned char data) { while((UART0_FR_R&0x0020) != 0); // wait until TXFF is 0 UART0_DR_R = data; Show how to convert to UART1 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

UART Interrupts UART0_IFLS_R register (bits 5,4,3)
RXIFLSEL RX FIFO Set RXRIS interrupt trigger when 0x0 ≥ ⅛ full Receive FIFO goes from 1 to 2 characters 0x1 ≥ ¼ full Receive FIFO goes from 3 to 4 characters 0x2 ≥ ½ full Receive FIFO goes from 7 to 8 characters 0x3 ≥ ¾ full Receive FIFO goes from 11 to 12 characters 0x4 ≥ ⅞ full Receive FIFO goes from 13 to 14 characters TXIFLSEL TX FIFO Set TXRIS interrupt trigger when 0x0 ≤ ⅞ empty Transmit FIFO goes from 15 to 14 characters 0x1 ≤ ¾ empty Transmit FIFO goes from 13 to 12 characters 0x2 ≤ ½ empty Transmit FIFO goes from 9 to 8 characters 0x3 ≤ ¼ empty Transmit FIFO goes from 5 to 4 characters 0x4 ≤ ⅛ empty Transmit FIFO goes from 3 to 2 characters Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Lab 9 – Distributed Measurement

Lab9: Transmitter SysTick ISR
Toggle heartbeat Sample ADC Convert to integer part of fixed point Send message, 8 calls to UART_OutChar STX Ones digit Decimal point Tenths digit Hundreds digit Thousandth digit CR ETX Busy-wait version Busy-wait version Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Lab9: UART Rx Interrupt Interrupt Trigger, sets RXRIS
Receive FIFO has gone from 7 to 8 elements (1/2 full) Initialization (add these) Arm RXRIS UART1_IM_R |= 0x10; Set UART1_IFLS_R bits 5,4,3 to 010 (1/2 full) NVIC_PRI1_R // bits 21-23 NVIC_EN0_R // enable interrupt 6 in NVIC Interrupt vector in startup.s Name ISR UART1_Handler Acknowledge (in ISR) UART1_ICR_R = 0x10; Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Lab9: Interrupt+Mailbox?
Background thread Foreground thread RXRIS ISR Read UART1_DR_R Store in RXmail Set RXstatus Main loop Wait for RXstatus Read RXmail Clear RXstatus Convert to distance Display on LCD If the receiver is too slow, that is if the processing of the foreground thread takes too long calling the LCD to display then the background thread could interrupt multiple times while the display is taking place and there is a potential to loose incoming data because there is only one slot in the RXmail mailbox. What can go wrong? Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

First-In/First-Out (FIFO) Queues
Order preserving Producer(s) put (on tail end) Consumer(s) get (from head end) Buffer decouples producer & consumer Even out temporary mismatch in rates Why is a queue needed? the short term information rates of the source and sink are unequal example: a network interface can supply information at 108 b/s while the disk that is receiving the information can process it at only 106 b/s Why use a FIFO the processing for the source can be separated from the processing of the sink FIFO to even out variations in rate between producer and consumer. As long as: Maximum producer rate is less than latency Average producer rate is less than average consumer rate How are source and sink processing separated? the source writes information into the buffer* (queue) at the location specified by a pointer called IN(put) while the sink reads information from the buffer at the location specified by a pointer called OUT(get) since the read and write operate with different variables, the source and sink can access the buffer independently (Alternative solution uses Count that both read/modify) *for our purposes, buffer and queue are equivalent Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO Operation I/O bound input interface

FIFO Operation High bandwidth input burst

FIFO Queue Synchronization
What should happen in Put/Get when FIFO is full/empty? -> Blocking vs. non-blocking: stall vs. return error -> In case of non-blocking/error, what to do? Throw away data/return dummy data and continue, or wait (repeatedly poll FIFO). No FIFO on transmitter side, using busy-wait synchronization: -> Ensure that SysTick interrupt doesn’t run faster than serial port FIFO on receiver side, using interrupt synchronization: -> Non-blocking Put (throw away data), blocking Get (poll FIFO until data) Lab 9 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Lab 9 - RXRIS ISR toggle PF2 (change from 0 to 1, or from 1 to 0), heartbeat as long as the RXFE bit in the UART1_FR_R is zero Read bytes from UART1_DR_R Put all bytes into your software FIFO, RxFifo_Put Should be exactly 8 bytes, but could be more possibly If your software FIFO is full (data lost) increment a global error count (but don’t loop back) The message will be interpreted in the main program Increment a Counter, debugging monitor of the number of UART messages received acknowledge the interrupt by clearing the flag which requested it UART1_ICR_R = 0x10; // clears bit 4 (RXRIS) in RIS register return from interrupt Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO Queue Implementation
How is memory allocated? FIFO implies that we write new data at the head of the queue and we read data from the tail of the queue What problem does this cause? To address that problem the queue is operated in a circular manner An array of locations is processed so that the FIRST element of array appears to follow the LAST element of the array Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Two parameters are needed to specify the FIFO buffer (array) FIRST (usually index 0) points to the first location of the buffer LIMIT (usually index SIZE) points to last location+1 of the buffer since LIMIT is outside the buffer, data must not be written there FIRST and LIMIT are constants they are NOT modified by either the source or sink processing routines Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

PutPt: Points to the location where the next element to be added goes GetPt: Points to the location of the oldest valid element, hence the element to be removed first Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO Full/Empty Conditions
FIFO Parameter Relations Buffer is EMPTY PutPt equals GetPt Buffer is FULL PutPt + 1 equals GetPt note that there is no data stored at PutPt as a result, if N locations are allocated for a buffer, only N-1 data elements will fill the buffer Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO Wrapping Pointer wrap on 2nd put Pointer wrap on 4th get
FIRST Pointer wrap on 2nd put LIMIT FIRST Pointer wrap on 4th get LIMIT Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO Queue FIFO Implementations FIFO_Put FIFO_Get
stores a single value on the FIFO queue operates with interrupts disabled updates PutPt detects buffer full condition handles transition from LIMIT-1 to FIRST FIFO_Get reads a single value from the FIFO queue updates GetPt detects buffer empty condition Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO in C #define FIFO_SIZE 10 long static *PutPt; long static *GetPt;
long static Fifo[FIFO_SIZE]; void Fifo_Init(void){ PutPt = GetPt = &Fifo[0]; } static means private to this file Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO Routines in C Actually plus 4 bytes int Fifo_Put(long data) {
long *tempPt; tempPt = PutPt+1; // see if there is room if(tempPt==&Fifo[FIFO_SIZE]){ tempPt = &Fifo[0]; } if(tempPt == GetPt){ return(0); // full! else{ *(PutPt) = data; // save PutPt = tempPt; // OK return(1); Actually plus 4 bytes Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO Routines in C Actually plus 4 bytes int Fifo_Get(long *datapt) {
if(PutPt == GetPt){ return(0); // Empty } else { *datapt = *(GetPt++); if(GetPt==&Fifo[FIFO_SIZE]){ GetPt = &Fifo[0]; return(1); Actually plus 4 bytes Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO Queue – Index Implementation
FIFO Implementations FIFO_Put stores a single value on the FIFO queue operates with interrupts disabled updates PutI detects buffer full condition handles transition from LIMIT-1 to FIRST FIFO_Get reads a single value from the FIFO queue updates GetI detects buffer empty condition Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO in C – Index Implementation
static means private to this file #define FIFO_SIZE 10 long static PutI; //Index in FIFO to // put new item in long static GetI; //Index of oldest // item in FIFO long static Fifo[FIFO_SIZE]; void Fifo_Init(void){ PutI = GetI = 0; } Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO in C – Index Implementation
int Fifo_Put(long data) { if ( (PutI+1)% FIFO_SIZE) == GetI) { return(0); } FIFO[PutI] = data; PutI = (PutI+1)%FIFO_SIZE; return(1); int Fifo_Get(long *datapt) if (GetI == PutI) { *datapt = FIFO[GetI]; GetI = (GetI+1)%FIFO_SIZE; Full FIFO check Empty FIFO check Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FIFO Full Errors Average producer rate exceeds the average consumer rate Sample ADC every 50 ms Average time to process the sample is 51 ms Solution: decrease producer rate or increase consumer rate Lower sampling rate Faster computer More efficient compiler Rewrite time-critical code in assembly More computers (distributed processing) Producer rate temporarily exceeds the consumer rate Sample ADC every 50 ms Every 100th sample it takes 1 sec to process Solution: increase FIFO queue size Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Lecture 13: 2-D Arrays, Bitmaps, Sprites, Structs, Lab 10 Bard, Gerstlauer, Valvano, Yerraballi

Agenda Recap Agenda Lab9 UART, Interrupts FIFO Queues
Race Condition, Critical section Agenda Software design 2-D array Bitmaps Structs Lab 10 Bard, Gerstlauer, Valvano, Yerraballi

Software Design Modular programming Make it easier to understand
Each screen is a complete story without scrolling Maximize the number of modules Minimize the interdependency Bandwidth of data passed from one to another Control coupling: actions in one cause effects in another Shared variables (very bad) Book Section 5.2 Bard, Gerstlauer, Valvano, Yerraballi

Software Design Design for test Manage resources
Consider how it will be tested while designing Module has three files Header: What the module does Code: How it works Test: A main program used to test the module Manage resources LCD graphics Time (processor cycles) A fun game requires careful control of time Input/Output Switches, slide pot, DAC, LCD Bard, Gerstlauer, Valvano, Yerraballi

2-D Array or Matrix What: 2 rows and 3 columns, 8 bits each Why:
unsigned char M[2][3]; Why: Images Maps How: (C uses row major) C code to access M[i][j] = 5; Write this in assembly (R0=i, R1=j) i = row j = column n= # of columns Base+n*i+j Base+2*(n*i+j) Base+4*(n*i+j) Num of bytes/element Bard, Gerstlauer, Valvano, Yerraballi

2-D Array or Matrix j i What: 6 rows and 7 columns Why:
short Connect4[6][7]; Why: Images Maps How: (row major) Write C code to set array values to 0 Write in assembly i Base+2*(7*i+j) Bard, Gerstlauer, Valvano, Yerraballi

2-D Array or Matrix j i Assuming C[6][7] // check the rows
for(i=0;i<6;i++){ for(j=0;j<4;j++){ if((C[i][j]==1) &&(C[i][j+1]==1) &&(C[i][j+2]==1) &&(C[i][j+3]==1)){ Iwin(); } i 0 means free 1 means me -1 means you Bard, Gerstlauer, Valvano, Yerraballi

Kentec Graphics Format
Column 0 Row 0 Row 239 LCD is 240 rows, 320 columns, 16 bits/pixel Column 319 Bard, Gerstlauer, Valvano, Yerraballi

4-bit (16-color) Palette // Map 4-bit color to 16-bit color: red,green,blue // bits bit red // bits bit green // bits bit blue unsigned short const Color4[16] = { 0, //0 – black ((0x00>>3)<<11) | ((0x00>>2)<<5) | (0xAA>>3), //1 – blue ((0x00>>3)<<11) | ((0xAA>>2)<<5) | (0x00>>3), //2 – green ((0x00>>3)<<11) | ((0xAA>>2)<<5) | (0xAA>>3), //3 – cyan ((0xAA>>3)<<11) | ((0x00>>2)<<5) | (0x00>>3), //4 – red ((0xAA>>3)<<11) | ((0x00>>2)<<5) | (0xAA>>3), //5 – magenta ((0xAA>>3)<<11) | ((0x55>>2)<<5) | (0x00>>3), //6 – brown ((0xAA>>3)<<11) | ((0xAA>>2)<<5) | (0xAA>>3), //7 – light gray ((0x55>>3)<<11) | ((0x55>>2)<<5) | (0x55>>3), //8 – dark gray ((0x55>>3)<<11) | ((0x55>>2)<<5) | (0xFF>>3), //9 – bright blue ((0x55>>3)<<11) | ((0xFF>>2)<<5) | (0x55>>3), //10 – bright green ((0x55>>3)<<11) | ((0xFF>>2)<<5) | (0xFF>>3), //11 – bright cyan ((0xFF>>3)<<11) | ((0x55>>2)<<5) | (0x55>>3), //12 – bright red ((0xFF>>3)<<11) | ((0x55>>2)<<5) | (0xFF>>3), //13 – bright magenta ((0xFF>>3)<<11) | ((0xFF>>2)<<5) | (0x55>>3), //14 – bright yellow ((0xFF>>3)<<11) | ((0xFF>>2)<<5) | (0xFF>>3) //15 – bright white }; #define BURNTORANGE 0xCB01 // R=197/8 G=96/2 B=6/8 Use 4-bit color to reduce code size, still fits in 32k Bard, Gerstlauer, Valvano, Yerraballi

BMP File Format Sprites as objects moving across screen
SmallEnemy sprites are 16-color, 16 pixels wide by 10 pixels high Alien sprites are 16-color, 32 pixels wide by 20 pixels high Bard, Gerstlauer, Valvano, Yerraballi

BMP File Format LCD_DrawBMP(SmallEnemy10pointA,50,100);
16 wide, 10 high Placed at x=50, y=100 F F F F FFFFFFFFFF FFFFFFFFFFFF FFF FFFF FFF F FFFFFFFF F F F F F The raw data from BMP file to illustrate how the image is stored (0s replaced with spaces). Bard, Gerstlauer, Valvano, Yerraballi

BMP File Format Example BMP file written as C constant Header (w x h)
const unsigned char Enemy10Point1[] = { 0x42,0x4D,0xC6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x76,0x00,0x00,0x00,0x28,0x00, 0x00,0x00,0x10,0x00,0x00,0x00,0x0A,0x00,0x00,0x00,0x01,0x00,0x04,0x00,0x00,0x00, 0x00,0x00,0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x80, 0x00,0x00,0x00,0x80,0x80,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x80,0x00,0x80,0x80, 0x00,0x00,0x80,0x80,0x80,0x00,0xC0,0xC0,0xC0,0x00,0x00,0x00,0xFF,0x00,0x00,0xFF, 0x00,0x00,0x00,0xFF,0xFF,0x00,0xFF,0x00,0x00,0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF, 0x00,0x00,0xFF,0xFF,0xFF,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x0F,0x00,0x00,0x00,0x00,0xF0,0x00, 0x00,0x00,0xF0,0x00,0x00,0x0F,0x00,0x00, 0x00,0x0F,0xFF,0xFF,0xFF,0xFF,0xF0,0x00, 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00, 0x00,0xFF,0xF0,0xFF,0xFF,0x0F,0xFF,0x00, 0x00,0xF0,0xFF,0xFF,0xFF,0xFF,0x0F,0x00, 0x00,0xF0,0x0F,0x00,0x00,0xF0,0x0F,0x00, 0xFF }; Example BMP file written as C constant Header (w x h) Pixel data We can use either 24-bit BMP or 4-bit BMP Bard, Gerstlauer, Valvano, Yerraballi

Structure Definition One object Collection of data
Data has dissimilar types or meanings struct State { unsigned long x; // x coordinate unsigned long y; // y coordinate const unsigned char *image; // ptr->image long life; // 0=dead, 1=alive }; typedef struct State STyp; a new type Bard, Gerstlauer, Valvano, Yerraballi

Structure Creation Put in RAM if data changes
Initialized at run time, before main() the new type STyp Enemy[18]={ {0,10, SmallEnemy30PointA,1}, {20,10, SmallEnemy30PointA,1}, {40,10, SmallEnemy30PointA,1}, {60,10, SmallEnemy30PointA,1}, {80,10, SmallEnemy30PointA,1}, {100,10, SmallEnemy30PointA,1}, … {100,30, SmallEnemy10PointA,1} }; Bard, Gerstlauer, Valvano, Yerraballi

Structure Creation Put in RAM if data changes
Run-time initialization inside main() STyp Enemy[18]; void Init(void){ int i; for(i=0;i<6;i++){ Enemy[i].x = 20*i; Enemy[i].y = 10; Enemy[i].image = SmallEnemy30PointA; Enemy[i].life = 1; } Bard, Gerstlauer, Valvano, Yerraballi

Structure Example Student database Structure definition
Set of student records Structure definition struct Student { char Initials[2]; short id; struct Student *teammate; }; typedef struct Student SType; Bard, Gerstlauer, Valvano, Yerraballi

Arrays of Structures Pointers to specific elements
Array of structure creation #define XYpt &class[0] #define ABpt &class[1] #define RSpt &class[2] ... SType class[6] = { {{'X','Y'},123, RSpt}, // XY {{'A','B'}, 23, RYpt}, // AB {{'R','S'}, 11, XYpt}, // RS {{'R','Y'},2457, ABpt}}; // RY Bard, Gerstlauer, Valvano, Yerraballi

Arrays of Structures Traverse array Add features Seating chart
Write a function to place a student into seat Write code to navigate through the class array and print all student records in the following format: FI-LI : id (team-mate_id) SType seatChart[5][24]; //2-D array Bard, Gerstlauer, Valvano, Yerraballi

Timer 2A Periodic interrupt
Resolution: bus period Precision: 32 bits Max period: 53 sec (80 MHz) 0) activate timer2 clock 1) disable timer2A 2) Precision to 32 bits 3) periodic mode 4) TAILR value 5) clock resolution 6) clear timeout flag 7) arm timeout 8) priority 4 9) enable in NVIC 10) enable timer2A Bard, Gerstlauer, Valvano, Yerraballi

77 total INTERRUPT VECTORS Bard, Gerstlauer, Valvano, Yerraballi Lab 7
Vector address Number IRQ ISR name in Startup.s NVIC Priority bits 0x 14 -2 PendSV_Handler NVIC_SYS_PRI3_R 23 – 21 0x C 15 -1 SysTick_Handler 31 – 29 0x 16 GPIOPortA_Handler NVIC_PRI0_R 7 – 5 0x 17 1 GPIOPortB_Handler 15 – 13 0x 18 2 GPIOPortC_Handler 0x C 19 3 GPIOPortD_Handler 0x 20 4 GPIOPortE_Handler NVIC_PRI1_R 0x 21 5 UART0_Handler 0x 22 6 UART1_Handler 0x C 23 7 SSI0_Handler 0x 24 8 I2C0_Handler NVIC_PRI2_R 0x 25 9 PWMFault_Handler 0x 26 10 PWM0_Handler 0x C 27 11 PWM1_Handler 0x 28 12 PWM2_Handler NVIC_PRI3_R 0x 29 13 Quadrature0_Handler 0x 30 ADC0_Handler 0x C 31 ADC1_Handler 0x 32 ADC2_Handler NVIC_PRI4_R 0x 33 ADC3_Handler 0x 34 WDT_Handler 0x C 35 Timer0A_Handler 0x 36 Timer0B_Handler NVIC_PRI5_R 0x 37 Timer1A_Handler 0x 38 Timer1B_Handler 0x C 39 Timer2A_Handler 0x000000A0 40 Timer2B_Handler NVIC_PRI6_R 0x000000A4 41 Comp0_Handler 0x000000A8 42 Comp1_Handler 0x000000AC 43 Comp2_Handler 0x000000B0 44 SysCtl_Handler NVIC_PRI7_R 0x000000B4 45 FlashCtl_Handler 0x000000B8 46 GPIOPortF_Handler 0x000000BC 47 GPIOPortG_Handler 0x000000C0 48 GPIOPortH_Handler NVIC_PRI8_R 0x000000C4 49 UART2_Handler 0x000000C8 50 SSI1_Handler 0x000000CC 51 Timer3A_Handler 0x000000D0 52 Timer3B_Handler NVIC_PRI9_R 0x000000D4 53 I2C1_Handler 0x000000D8 54 Quadrature1_Handler 0x000000DC 55 CAN0_Handler 0x000000E0 56 CAN1_Handler NVIC_PRI10_R 0x000000E4 57 CAN2_Handler 0x000000E8 58 Ethernet_Handler 0x000000EC 59 Hibernate_Handler 0x000000F0 60 USB0_Handler NVIC_PRI11_R 0x000000F4 61 PWM3_Handler 0x000000F8 62 uDMA_Handler 0x000000FC 63 uDMA_Error Lab 7 Lab 8 Lab 9 77 total INTERRUPT VECTORS Bard, Gerstlauer, Valvano, Yerraballi

Timer 2A Periodic interrupt
Max is 53 sec unsigned long TimerCount; void Timer2_Init(unsigned long period){ unsigned long volatile delay; SYSCTL_RCGCTIMER_R |= 0x04; // 0) activate timer2 delay = SYSCTL_RCGCTIMER_R; TimerCount = 0; TIMER2_CTL_R = 0x ; // 1) disable timer2A TIMER2_CFG_R = 0x ; // 2) 32-bit mode TIMER2_TAMR_R = 0x ; // 3) periodic mode TIMER2_TAILR_R = period-1; // 4) reload value TIMER2_TAPR_R = 0; // 5) clock resolution TIMER2_ICR_R = 0x ; // 6) clear timeout flag TIMER2_IMR_R = 0x ; // 7) arm timeout NVIC_PRI5_R = (NVIC_PRI5_R&0x00FFFFFF)|0x ; // 8) priority 4 NVIC_EN0_R = 1<<23; // 9) enable IRQ 23 in TIMER2_CTL_R = 0x ; // 10) enable timer2A } Output sound at kHz Bard, Gerstlauer, Valvano, Yerraballi

Timer 2A plays sounds TATORIS Ack Output sounds here Stuff
// trigger is Timer2A Time-Out Interrupt // set periodically TATORIS set on rollover void Timer2A_Handler(void){ TIMER2_ICR_R = 0x ; // acknowledge TimerCount++; // run some background stuff here } void Timer2A_Stop(void){ TIMER2_CTL_R &= ~0x ; // disable void Timer2A_Start(void){ TIMER2_CTL_R |= 0x ; // enable TATORIS Ack Output sounds here Stuff Call to stop sound Call to start sound Bard, Gerstlauer, Valvano, Yerraballi

Lab 10 – Connect Four There must be at least one button and one slide pot. The colored pieces must move on the LCD. There must be sounds appropriate for the game. The score should be displayed on the screen (but it could be displayed before or after the game action). At least two interrupt ISRs must used in an appropriate manner. The game must have a man versus machine mode. Bard, Gerstlauer, Valvano, Yerraballi

Lab10 – Space Invaders, Pipe Dreams …
There must be at least one button and one slide pot. There must be at least three images on the LCD display that move. There must be sounds appropriate for the game. The score should be displayed on the screen (but it could be displayed before or after the game action). At least two interrupt ISRs must used in an appropriate manner. The game must have a “time” aspect to it (For e.g., if you don’t move a sprite within a certain time it could be killed). Contrast with ConnectFour which is a taking “turns” game The game must be both simple to learn and fun to play. Bard, Gerstlauer, Valvano, Yerraballi

Lab 10 – Grading The TAs will sort into groups and certify requirements Show game to TA before class on 4/30 or 5/1 Wonderful group will have max of 100 points Supreme group will have a max of 120 points Lab 10 will be graded subjectively by other students During class on 4/30 or 5/1 meet in ENS507 One team member demonstrates The other team member scores other games Groups of one are checked out by the TA Can’t compete unless both members are present Games are rank-ordered according to level of fun Superfinals Friday 5/ in ENS507 Bard, Gerstlauer, Valvano, Yerraballi

Lab 10 – Grading Wonderful group Supreme
80 if 0th to 49th percentile 90 if 50th to 74th percentile 100 if 75th to 100th percentile Supreme 100 if 0th to 49th percentile 110 if 50th to 74th percentile 120 if 75th to 100th percentile TA certification due date is 2 hours before the start of the last lecture class of the semester. 4/30 or 5/1 Late checkouts are handled by the TA in the usual way. All late checkouts must be completed by Friday 3pm, All LCDs with the bag must be returned by 5pm Friday. Bard, Gerstlauer, Valvano, Yerraballi

Lecture 14: Gaming Engines, Coding Style, Floating Point Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Agenda Recap Agenda Software design 2-D arrays, structs
Bitmaps, sprites Lab 10 Agenda Gaming engine design Coding style Floating point Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

(Adapted from V. Aagrawal)
Numbers Integers (ℤ): universe is infinite but discrete No fractions No numbers between 5 and 6 A countable (finite) number of items in a finite range Real numbers (ℝ): universe is infinite & continuous Fractions represented by decimal notation Rational numbers, e.g., 5/2 = 2.5 Irrational numbers, e.g., p ~ 22/7 = Infinity of numbers exist even in the smallest range (Adapted from V. Aagrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Number Representation
Integers Fixed-width integer number Reals Fixed-point number  I •  Store I, but  is fixed Decimal fixed-point (=10m) = I • 10m Binary fixed-point (=2m) = I • 2m Floating-point number = I • BE Store both I and E (only B is fixed) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Wide Range of Real Numbers
A large number: 976,000,000,000,000 = 9.76 • 1014 A small number: = 9.76 • No fixed  that can represent both Not representable in single fixed-point format (Adapted from V. Aagrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Floating Point Numbers
Decimal scientific notation 0.513×105, 5.13×104 and 51.3×103 5.13×104 is in normalized scientific notation Binary floating point numbers Base B = 2 Binary point Multiplication by 2 moves the point to the left Normalized scientific notation, e.g., 1.0×2-1 Known as floating point numbers (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

(Adapted from V. Agrawal)
Normalizing Numbers In scientific notation, we generally choose one digit to the left of the decimal point 13.25 × 1010 becomes × 1011 Normalizing means Shifting the decimal point until we have the right number of digits to its left Normally one Adding or subtracting from the exponent to reflect the shift (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Floating Point Numbers
General format ±1.bbbbb two×2eeee or (-1)S × (1+F) × 2E Where S = sign, 0 for positive, 1 for negative F = fraction (or mantissa) as a binary integer, F is called significand E = exponent as a binary integer, positive or negative (two’s complement) (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

ANSI/IEEE Std Single-precision float format Bit 31 Mantissa sign, s=0 for positive, s=1 for negative Bits 30:23 8-bit biased binary exponent 0 ≤ e ≤ 255 Bits 22:0 24-bit mantissa, m, expressed as a binary fraction, A binary 1 as the most significant bit is implied. m = 1.m1m2m3...m23 (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

IEEE 754 Floating Point Standard
Biased exponent: exponent range [-127,127] changed to [0, 255] Biased exponent is an 8-bit positive binary integer True exponent obtained by subtracting or 255 = special case First bit of significand is always 1: ± 1.bbbb b × 2E 1 before the binary point is implicitly assumed So we don’t need to include it – just assume it’s there! Significand field is 23 bit fraction after the binary point Significand range is [1, 2) Standard formats: Single precision: 8 (E) + 23 (F) + 1 (S) = 32 bits (float) Double precision: 11 (E) + 52 (F) + 1 (S) = 64 bits (double) (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Numbers in 32-bit Formats
Two’s complement integers Floating point numbers The range is larger, but the number of numbers per unit interval is less than that for a comparable fixed point range Expressible numbers -231 231-1 Positive underflow Negative underflow Negative Overflow Expressible negative numbers Expressible positive numbers Positive Overflow -2-127 2-127 - (2 – 2-23)×2127 (2 – 2-23)×2127 (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Binary to Decimal Conversion
Binary (-1)S (1.b1b2b3b4) × 2E Represents (-1)S × (1 + b1×2-1 + b2×2-2 + b3×2-3 + b4×2-4) × 2E Example: × 2-2 (binary) = - ( ) ×2-2 = - ( )/4 = /4 = (decimal) (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Decimal to Binary Conversion
Converting from base 10 to the representation Single precision example Covert 10010 Step 1 – convert to binary In a binary representation form of 1.xxx have = x 26 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Decimal to Binary Conversion (cont’d)
x is binary for 100 Thus the exponent is a 6 Biased exponent will be 6+127=133 = Sign will be a 0 for positive Stored fractional part f will be 1001 Thus we have S E F …. C in hexadecimal $42C is representation for 100 Another example: Representation for -175 175 = = Or x 27 S = 1 Exponent is = 134 = Fractional part f = Representation …. Or in hex $C32F 0000 Convert floating point $C32F 0000 back into decimal: Extract components from Exponent = = = 134 unbias – 127 =7 f = so mantissa is Adjust by exponent (move binary pt 7 places) Or = 175 Sign is negative so -175 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Positive Zero in IEEE 754 Biased exponent Fraction + 1.0 × 2-127 Smallest positive number in single-precision IEEE 754 standard. Interpreted as positive zero. Exponent less than -127 is positive underflow; can be regarded as zero. (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Negative Zero in IEEE 754 Biased exponent Fraction - 1.0 × 2-127 Smallest negative number in single-precision IEEE 754 standard. Interpreted as negative zero. True exponent less than -127 is negative underflow; may be regarded as 0. (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Positive Infinity in IEEE 754
Biased exponent Fraction + 1.0 × 2128 Largest positive number in single-precision IEEE 754 standard. Interpreted as + ∞ If true exponent = 128 and fraction ≠ 0, then the number is greater than ∞. It is called “not a number” or NaN and may be interpreted as ∞. (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Negative Infinity in IEEE 754
Biased exponent Fraction -1.0 × 2128 Smallest negative number in single-precision IEEE 754 standard. Interpreted as - ∞ If true exponent = 128 and fraction ≠ 0, then the number is less than - ∞ It is called “not a number” or NaN and may be interpreted as - ∞. (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

IEEE Representation Values
If E=255 and F is nonzero, then V=NaN ("Not a number") If E=255 and F is zero and S is 1, then V=-Infinity If E=255 and F is zero and S is 0, then V=+Infinity If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1.F) where "1.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. If E=0 and F is nonzero, then V=(-1)**S * 2 ** (-126) * (0.F) These are "unnormalized" values. If E=0 and F is zero and S is 1, then V=-0 If E=0 and F is zero and S is 0, then V=0 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Addition and Subtraction
0. Zero check - Change the sign of subtrahend - If either operand is 0, the other is the result 1. Significand alignment: right shift smaller significand until two exponents are identical. 2. Addition: add significands and report exception if overflow occurs. 3. Normalization - Shift significand bits to normalize. - report overflow or underflow if exponent goes out of range. 4. Rounding (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Rounding Adjusting significands before addition will produce results that exceed 24 bit Round toward infinity select next largest normalized result Round toward minus infinity select next smallest normalized result Round toward zero truncate result Round to nearest select closest normalized result used by IEEE 754 Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

Example Subtraction: Step 0: Floating point numbers to be added 1.0002×2-1 and ×2-2 Step 1: Significand of lesser exponent is shifted right until exponents match ×2-2 → ×2-1 Step 2: Add significands, ( ) Result is ×2-1 Step 3: Normalize, × 2-4 No overflow/underflow since 127 ≥ exponent ≥ -126 Step 4: Rounding, no change since the sum fits in 4 bits. ×2-4 = (1+0)/16 = (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FP Multiplication: Basic Idea
Separate sign Add exponents Multiply significands Normalize, round, check overflow Replace sign (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

FP Division: Basic Idea
Separate sign. Check for zeros and infinity. Subtract exponents. Divide significands. Normalize/overflow/underflow. Rounding. Replace sign. (Adapted from V. Agrawal) Bill Bard, Andreas Gerstlauer, Jon Valvano, Ramesh Yerraballi

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