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ARM Cortex M3 & M4 Chapter 4 - Architecture
RTLAB Wi Daehan
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INDEX Operation modes and states Registers Special registers
Floating point registers Behavior of the APSR (Application program status register) Memory system Exceptions & Interrupts SCB (System control block) Reset & Reset sequence
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Operation modes and states
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Registers R0 – R12 R13, stack pointer (SP) R14, link register (LR)
R15, program counter (PC)
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Special registers Program status registers MASK registers
CONTROL register
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Special registers Program status registers
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Special registers Program status registers
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Special registers MASK registers
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Special registers CONTROL register
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Floating point registers
Single precision operation Define floating point operation behaviors Provide status information about operation results
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Behavior of the APSR APSR contains status flags
Integer operations (N-Z-C-V bits) Saturation arithmetic (Q bit) SIMD operations (GE bits)
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Behavior of the APSR Integer status flags
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Behavior of the APSR Q status flag
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Behavior of the APSR GE bits
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Memory system Memory system features 4GB linear address space
Architecturally defined memory map Support for little endian and big endian memory systems Write buffer Memory Protection Unit (Optional) Unaligned transfer support
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Memory system Memory map
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Exceptions & Interrupts
Various exception sources
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Exceptions & Interrupts
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Exceptions & Interrupts
Nested vectored interrupt controller (NVIC) Flexible exception and interrupt management Nested exception/interrupt support Vectored exception/interrupt entry Interrupt masking
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Exceptions & Interrupts
Vector table
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Exceptions & Interrupts
Fault handling
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SCB (System control block)
Merged into the NVIC Controlling processor configurations (e.g., low power modes) Providing fault status information (fault status registers) Vector table relocation (VTOR)
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Reset & Reset sequence Power on reset - reset everything in the microcontroller. System reset - reset just the processor and peripherals. Processor reset - reset the processor only.
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Reset & Reset sequence
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Reset & Reset sequence
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