1. Selling The Value Of Software
Fall 1998 Worldwide
Sales Force Training

2. Agenda What Is The Value Of Software? Why Charge For Software?
Where Is The Value In Version 1.5?
What Is Beyond 1.5? (Release Roadmap)
Overcoming Objections And Sales Tips
Summary

3. What Do We Mean By “Sell The Value Of Software”?
Selling the value means raising the perceived value or worth of the product in the eyes of the buyer
it does not mean just getting more money for it!

4. Why Charge For Software?
It helps qualify the account. If software were free, we might spend time with prospects that may not have a need for programmable logic.
The customer has a budget to spend. It’s typically the first allocation of funds on the project and it subsidises FAE effort. If we don’t take it, Altera will!
The customer will value it more. The more a customer invests in software, the less likely he is to abandon it later.

5. Why Sell The Value? 1) The more a customer values his software/Core:
The more likely he is to use Xilinx instead of the competition.
The less likely he is to drop maintenance.
The more seats he’ll buy!
2) Software is a Fundamental part of the solution!
Software and cores are playing a more strategic role in the customer’s programmable logic vendor choice.
3) It’s NOW a competitive advantage! Sell Components + Software/Cores + Support.

6. Why Sell Maintenance?
An in-maintenance customer is much more likely to choose Xilinx next time!
Immediate visibility to best components.
Immediate visibility to best software.
Ability to evaluate Xilinx solution first.
Customer doesn’t have to pay anything before starting their design.

7. Where Is The Value In Software
Where Is The Value In Software? Customers see value in software that will enable them to get their job done in the fastest possible time.
Mainstream designer Productivity is dependent on:
Ease-of-Use
Run Time
High density and high speed designer Productivity is dependent on:
User Control
Design Performance
Design Iteration Time - Run Time
Productivity through Ease-of-Use, Performance Driven Design, and User Control.

8. Where’s the Value in 1.5? Ease of Use
Constraints Editor
Simple control over powerful constraints
Automatic Pin Locking
When you’re ready for board layout
Instant Software Access
No waiting for license
Improved Reporting
Important information first

9. Graphical Constraints Editor
What won’t CE do? What arethegotchas for 1.5 (with the caveat that itwill evolve over time)
Guides user to the best constraint methodology

10. Where’s the Value in 1.5? Performance
Minimum Delays
Allows for system level race checking
Temperature and Voltage Prorating
Faster performance at more optimal operating conditions
Automatic Clock Skew Handling
Accounts for clock skew in performance driven designs
Dramatic Improvements to PAR

11. Where’s the Value in 1.5? Performance - PAR Improvements
Average 2-3x runtime improvement, 10x on some designs
Faster timing analysis with K-path algorithm
Achieves higher clock rates more easily
hits timespecs more often
Low Utilization designs will route much more quickly
Better performance on high fanout nets
new high fanout router
All this means….
More Turns Per Day Faster Design Cycles

12. Competitive Benchmarks
Runtime in Minutes
Performance in MHz
Default
42% 4%
44% 3% 9%
20 HDL designs ranging from 5K to 100K gates
XC4000XL-08 vs. 10KA-1, Alliance Series 1.5 vs. Max+PLUS II v9.01
Runtimes are place and route only on 400MHz Pentium II

13. Where’s the Value in 1.5? User Control
Floorplanner
Area or detailed layout
New Constraints
Global IO timing
TNM_NET for synthesis designs
Push Button Performance
Simple control over tradeoff between runtime and performance

14. Graphical Floorplanner
Add knowledge of the designs structure to increase performance up to 40%
Area constraints for modules provide
faster runtimes
higher performance
design changes made easier

15. Foundation & Alliance Series Unparalleled Productivity Key Features in Version 1.5
4 New FPGA/CPLD Families
50% Runtime Reduction
Graphical Constraints Editor
Floorplanner
Automatic Pin Locking
6x Faster Timing Analysis (Kpaths algorithm)
Automatic Clock Skew Handling
New Reporting of Minimum Delays
Voltage and Temperature Speed Pro-rating
Instant Software Access
The goal of this slide is to provide additional details about Xilinx’ upcoming
software release which combined with the 1.4 compile time improvements provides over an order of magnitude faster compile times over In additional Xilinx is releasing features in the 1.5 release which won’t be available from the competition for at least another year.

16. Release Roadmap
Service Packs Incorporate the accumulation of all bug fixes from one major release to the next.

17. Contents of Performance Pack 1.5i
Get new (faster) speeds into software
XC4000XLA & XV -08, Virtex -6
Tune PAR with updated speeds files
Auto timespecing
Roll all bug fixes into a fully SQA tested environment
Enhance Virtex and Constraints Editor quality
Support for IOB TBUF Reg in XLA/XV/SpartanXL
Improves output speed

18. Future Direction Responding to the Changing Landscape
Evolution of FPGA Design
Cores, Synthesis,
Design reuse,
Behavioral compiler
Larger design teams
Schematic
Single designer
Synthesis
Single designer
Synthesis and Cores
Small team
TIMELINE
Timing Driven PAR
HDL Back
Annotation
Tighter ties with synthesis vendors
Module Compile
Module
Guide
Team Based Design
Evolution of FPGA Tools

19. Modular Design Xilinx is Leading the Way
Facilitates Group Design & Reuse
Seamless Integration Between Modules
Extension to leading cores solution
Modular Time Specs
With industry’s best timing constraint language
Modular Incremental Compile
Extensive R&D investment
Designer1
Module
Designer2
Module
Designer3
Module
Design
Reuse
As designs get larger and people move toward system on a chip device, their designs will not consist of just random gates. They will consist of Cores, modules from old designs, and new modules created by different designers.
Integration between these modules is extremely important.
The ability to generate timing requirements for each module must be added to the software.
By separating the task into modules, each one can be compiles separately which will produce shorter compile times and high performance.
The foil above is a good example of how a large design is created. Multiple cores and multiple designers to design portions of the device. Xilinx deliver software solutions that help design, manage, and integrate these modules.
Reduces Compile Time & Increases Performance

20. Compile Time Leadership50 40
Up to 3X faster than 1.4 30
Minutes* 20 10
2002
Although in some situations a sales person may hesitate to show this slide based on customer perception, the goal of this slide is to take a step toward changing this perception. Xilinx clearly leads, when it comes to high performance design and timing driven compiles, and we are consistently beating our competition at various benchmarks. We may not always win, but we are definitely competitive and are in a good position to lead in many situations.
Notes: Average compile time for a 100,000 gate design in 1.3 was only about 400 gates per minute. In 1.4, that improved to 2000 gates per minute and has improved to over 4000 gates per minute in the 1.5 release. It is reasonable to assume that continued compile time improvements will achieve around 6000 gates per minute next year.
Assume that CPUs increase at about 2X per year means that 100,000 gates would take slightly over 8 minutes.
Plus the fact that module based compile means a linear increase in compile time as gate count increases.
Therefore, 1,000,000 = 10 modules of 100,000 8 min = 80 minutes.
With further advancements, we expect to keep the compile time of 10,000,000 gate designs to under 1 hour by the year 2002.
1998
1999
2000
2001
* 100k System gate designs (400MHz Pentium)
And with ...
Faster CPUs
Faster Compile Times
Modular Compile
1999 Goal:
1 Million Gates in under 1.5 hours!

21. Overcoming Objection #1
“I’m buying $$$ of your components; I’m not paying for software!”
How to answer the buyer who raises that objection:
Xilinx makes a major investment in software every year, if we didn’t subsidise that with software sales we’d have to increase the cost of the components. As a big component buyer, would you want that?
How to answer the engineer who raises that objection:
Xilinx and our partners offer the best Hotline and FAE support in the world and software revenue subsidises their effort.
Xilinx invests your software dollars not only in incremental improvements to the software but also in developing capabilities beyond push button implementation.

22. Overcoming Objection #2
“Altera gave me their software for free, why won’t Xilinx?” [Remember - Altera gets more $ per seat than we do!]
What the customer probably means is:
They gave me free evaluation s/w (PLS-WEB) or
They gave me one free seat for every two that I bought or
They gave me the entry software for free but I had to buy maintenance after 3 months and upgrades to get my design done.

23. Overcoming Objection #3
“How can you justify such a high price for your software?”
Xilinx offers software starting at $95 for Foundation and Alliance Base and a full VHDL and Verilog solution in Foundation Base X for only $495.
Royalties for ‘best in class’ partner software.
1st year’s maintenance included with Standard Packages.
Subsidise world-class distributor FAE support .
Buying the same tools on the open market would cost much more (e.g.. Foundation Express would cost $16,000 with Xilinx libraries).

24. Overcoming Objection #4
“Altera’s software is easy to use, why should I invest the time to learn Xilinx software?”
Yes, pushing a button is easy but, what if it doesn't do what you want? What if you want a cheaper (I.e. smaller or slower) component? Then you’ll need more powerful software.
If you want to learn an HDL design methodology you'll find Foundation Express gives you a very short learning curve.
A couple of hours spent learning our tools will save you many times that number of hours in timing driven compilation time!

25. Key Value Messages For Alliance?
Standards Based Design Interfaces
Allows customers to work in their chosen EDA environment.
A.K.A.speedtm TECHNOLOGY
Faster compile times and increased clock speed lets customers meet their specifications and get their product to market more quickly.
Integrated Core Generator Software And LogiBLOX
Customers can achieve higher performance and get their designs done faster.
World Class Technical Support
Instant support over the Web and via the phone to assist customers in completing designs.

26. Key Value Messages For Foundation?
Complete Front-To-Back Design Environment
The tightly integrated tool set makes it easy for customer to learn and use the tools.
Powerful VHDL And Verilog Synthesis - Synopsys FPGA Express
Robust language support and optimization technology allows customers to get the most speed out of their design.
Graphical HDL Editor And Integrated Language Wizard
Simple graphical tools help to reduce the time it takes for customers to complete their design.
World Class Technical Support
Instant support over the Web and via the phone to assist customers in completing designs.

27. So, What Should You Do With This Information?
Sell the value - it’s worth the time!
Software Win the designer not just the design!
Maintenance Make sure your customer is plugged into the future!
Cores Lock the customer into Xilinx for the long term!

28. Appendix - Sales Tips
Get the customer hooked first - Sell them Base or Base X.
Understand the customer’s budget and fit the quote to it (e.g. project, maintenance or capital budget).
Sell to the department manager, not the project manager.
Always sell maintenance to the department manager or systems administrator.
When the customer wants to deal on prices, get something in return (e.g. design win, reference quote, multiple seats).
Sell Cores to lock out the competition for this and future designs.