1. SVT – SuperB Workshop – Annecy 16-19 March 2010
40 cm
30 cm
20 cm
Layer0
old beam pipe
new beam pipe
SVT Update
Layer0 Strategy
Striplets baseline option for TDR:
Better physics performance (lower material) even with some inefficiency, due to high background conditions.
Upgrade to pixel (Hybrid or CMOS MAPS), more robust against background, is foreseen for a second generation of Layer0
Very challenging to keep the material for a pixel system at the level of the striplets (~0.5%X0)
R&D continue on various pixel items: CMOS MAPS, high rate readout electronics, low material support with cooling.
Need IR and SVT mechanics designed for a rapid replacement of Layer0.
Most of the activity on these items since Dec. Workshop
G. Rizzo
SVT – SuperB Workshop – Annecy March 2010

2. SVT – SuperB Workshop – Annecy 16-19 March 2010
R&D on pixel options
Hybrid pixel:
Prototype Front-end chip for hybrid pixel produced and under test since last Friday (F.Morsani-G.Casarosa):
Data push fast readout architecture
Target hit rate 100MHz/cm2
32x128 pixels, 50x50 um pitch.
Delay in the delivery of the pixel sensor matrix:
Still in production ready by Mid April
It might be difficult to realize bump bonding with the FE chip and get ready for the testbeam foreseen in Sept <-- Need to contact IZM Berlin asap
CMOS MAPS:
Campaign of irradiation with neutron started on APSEL test structures
Preparing next (~October) submission of 3D MAPS (realized with 2 CMOS layers interconnected, Chartered/Tezzaron 130 nm process).
Analog channel optimization. (V. Re’s Talk today)
New readout architecture under development with higher efficiency and better timestamp granularity (~100 ns) (F. Giorgi’s Talk today)
Still data push but could evolve easily to a triggered architecture
G. Rizzo
SVT – SuperB Workshop – Annecy March 2010

3. Miscellanea SVT activities
SVT Background Update – R.Cenci Wed.
C = 0.15% C0
Important material reduction (1/2) for pixel module support with active cooling
“Net module” Prototypes realized and tested
Results within specs up to 1.5 W/cm2
F.Bosi’s talk Wed.
Better definition of the SVT electronics (off detector)
M.Citterio’s talk Wed., F. Giorgi’s talk at the ETD session
FSSR2 (candidate chip for striplets and SVT) M.Bomben’s talk Wed.
Better noise characterization and new teststand in preparation in TS
Investigate efficiency vs occupancy with verilog simulation
Need an update soon!
G. Rizzo
SVT – SuperB Workshop – Annecy March 2010

4. UK Proposal for MAPS-based SVT
Queen Mary, RAL
Very interesting and well advanced MAPS technology from UK
INMAPS (180 nm) with deep p-well to improve CMOS sensor efficiency
Evolution of TPAC MAPS chip (50 mm pitch, realized for CALICE-ILC) being considered as a possible candidate for a MAPS all-pixel SVT.
G. Rizzo
SVT – SuperB Workshop – Annecy March 2010

5. UK Proposal for MAPS-based SVT
Queen Mary, RAL
PROS
Significantly cheaper than strip detector (large area, standard CMOS process)
Simpler module assembly
Very robust against background
CONS
Material of current proposal too large (1.14% X0 per layer instead of 0.5% X0)
New technology
Radiation hardness unproven
Need to evaluate physics potential of MAPS all-pixel SVT with FastSim studies:
include a realistic material budget for the support structure for all the layers with different geometries.
Had a very fruitful meeting in Pisa with UK proponents in March to discuss the proposal and share ideas on how to reduce the material budget for support with cooling in layers 1-5.
A.Bevan’s talk Wed.
G. Rizzo
SVT – SuperB Workshop – Annecy March 2010

6. TDR preparation (spring 2010!)
Questions to be answer during this Workshop:
What are the main technical questions that still need to be resolved for each system?
What is the essential R&D that is required to write the TDR?
When will it be completed?
What level of engineering,simulation, & design work is needed ?
What is the relationship between needs and the available resources?
Full technical details needed for baseline:
Layer0 with striplets
Layer1-5 strip detector
Describe the upgrade path for Layer0:
Status of the R&D on hybrid pixel and CMOS MAPS.
Depending on the evolution of the UK proposal in the next months include the MAPS all-pixel SVT.
G. Rizzo
SVT – SuperB Workshop – Annecy March 2010

7. SVT – SuperB Workshop – Annecy 16-19 March 2010
TDR – SVT Baseline
Layer0 with striplets (technology mature but need some work):
Background rate (including multiplicity) vs radius for 200 um thick sensor needed! (covered ?)
Is FSSR2 really adequate? (some manpower available but not enough!)
Readout efficiency vs occupancy study need to be complete
Simulation and possibly real measurement on chip.
Understand if small modifications are possible to improve readout performance and/or evaluate other existing chips.
Module assembly with multilayer fanout (still uncovered !)
HDI/transition card electronics (partly covered by M.Citterio assuming similar to pixel option…not enough!)
Layer1-5 strip detector:
Readout chip evaluation: FSSR2 modification needed for external layers (proposal to increase shaping time to 1 us. Evaluate impact!)
Module components: Si sensor/fanout/HDI
some manpower available in TS not enough!
SVT Mechanics:
Only 1 eng. available F.Bosi !!!
Very difficult to get new people involved with the present situation of the project!
G. Rizzo
SVT – SuperB Workshop – Annecy March 2010

8. TDR – SVT Upgrade Options
Pixel/new technology: more appealing manpower less critical. Synergy with R&D projects (not SuperB specific).
Describe the upgrade path for Layer0:
Status of the R&D on hybrid pixel and CMOS MAPS.
Plan for Hybrid Pixel quite clear
Schedule for testbeam is a pending issue: decision in the next few weeks.
Even without the testbeam lab characterization is possible and give info for TDR.
CMOS MAPS:
Proceed with the R&D (VIPIX Italian Collaboration):
Vertically integrated MAPS with 2 CMOS layers:
First chips should be ready by this summer (long delay in the production)
Next submission in October 2010 (results available for TDR?)
Layer0 mechanics well advanced.
G. Rizzo
SVT – SuperB Workshop – Annecy March 2010