1. Comparison Study of Bulk and SOI CMOS Technologies based Rad-hard ADCs in Space
Feitao Qi , Tao Liu , Hainan Liu , Chuanbin Zeng , Bo Li , Fazhan Zhao , Jiantou Gao , Gang Zhang , Jiajun Luo , Zhengsheng Han , and Zhongli Liu
Institute of Microelectronics of Chinese Academy of Sciences, Beijing , CHINA
Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences, Beijing , CHINA
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2. Overview INTRODUCTION SYSTEM ARCHITECTURE CIRCUITS DESIGN
IMECAS
INTRODUCTION
SYSTEM ARCHITECTURE
CIRCUITS DESIGN
HARDENED APPROACHES
EXPERIMENTAL RESULTS
CONCLUSION
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3. INTRODUCTION Harsh Space Environment: IMECAS Earth's radiation belts
Cosmic rays
Solar proton events
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4. INTRODUCTION Rad-hard SOI CMOS V.S. Bulk CMOS : IMECAS higher speed
(a)SOI CMOS
(b) Bulk CMOS
Rad-hard SOI CMOS V.S. Bulk CMOS :
higher speed
lower parasitic capacitance
smaller short channel effects
excellent capability of radiation hardness
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5. INTRODUCTION RHBD & RHBP IMECAS
Radiation Hardened by Design and Radiation Hardened by Process
A 10bits 25Msps high reliability pipelined ADC as a prototype
ADC
1992
Integrating analog to digital converter radiation hardness test technique and results
2006
Single-Event Sensitivity and Hardening of a Pipelined Analog-to-Digital Converter
2013
Radiation-Tolerant Code-Density Calibration of Nyquist-Rate Analog-to-Digital Converters
transistor level comparison
2002
Comparison of the sensitivity to heavy ions of 0.25-μm bulk and SOI technologies
Performance Comparison Between Bulk and SOI Junctionless Transistors
2014
Comparison of analog performance between SOI and Bulk pFinFET
circuit level comparison
This work
Comparison Study of Bulk and SOI CMOS Technologies based Rad-hard ADCs in Space
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6. INTRODUCTION
IMECAS
The bulk and SOI based CMOS ADC have identical schematic design and layout floor plan
The bulk CMOS technology and radiation hardened SOI CMOS technology have identical technology node
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7. SYSTEM ARCHITECTURE Sample and Hold Front-end 3+3+3+4 structure
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Sample and Hold Front-end
Extend the input bandwidth
structure
2.5bits/stage for first three stages
4bits/stage for last stage
Digital Correction Logic
Correct the error from comparators within the system redundancy
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8. CIRCUITS DESIGN Sample and Hold Circuit IMECAS
capacitor flip-around architecture
lower power consumption
better radiation hardness capability
Larger feedback factor
lower load capacitor
bottom plate sampling and bootstrapped switch
reduce the nonlinear effects of the switch
charge injection
clock feed through
improve the input bandwidth
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9. CIRCUITS DESIGN Sample and Hold Circuit Switched Capacitor Comparator
IMECAS
Sample and Hold Circuit
gain-boosted folded cascade amplifier
Effects of opamp caused by TID
gain and bandwidth reduction
DC offset increasing
efficiently improve the gain without reducing the bandwidth
Switched Capacitor Comparator
Switched Capacitor Comparator with a preamplifier
Low DC offset
wide input common mode range
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10. RADIATION HARDENED APPROACHES
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Hardened System and Circuits for ADC prototype
Properly determine and design system structure and circuits
the 2.5bits/stage system structure
the capacitor flip-around S/H
the gain-boosted folded cascade amplifier
the switched capacitor comparator with a preamplifier
Properly increase the current and capacitor value in sensitive parts
generates much smaller deviations when radiated
deviations from comparators will be corrected by the digital error correction logic
Hardened Layout for Bulk ADC
Mitigate the sensitivity of Single event Latch-up
Enough substrate contact around the transistor
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11. RADIATION HARDENED APPROACHES
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Radiation Hardened SOI CMOS Technology
Single event Latch-up Immunity
Join silicon dioxide on silicon substrate
SEU and SEFI sensitivity mitigation
Smaller charge collection volume
Other Radiation Hardened Measures
High level total ionizing dose radiation hardened
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12. EXPERIMENTAL RESULTS Electrical Experiment IMECAS
Table 1 Electrical Characteristics Comparison of SOI-based ADC and bulk CMOS ADC
SOI ADC
Bulk ADC
FS(Hz)
25M
Freq_vin(Hz) 2M
Supply（V） 5
Consumption（mw）
240
DNL(LSB)
±0.4
INL(LSB)
±0.5
SNR(dB)
60.5
59.6
SFDR(dB)
72.3
74.4
SINAD(dB)
60.2
59.2
ENOB(bits)
9.7
9.5
（a）SOI CMOS ADC
（b）Bulk CMOS ADC
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13. EXPERIMENTAL RESULTS Electrical Experiment IMECAS
SOI ADC exhibits better frequency characteristic
smaller parasitic capacitance
better I-V characteristic
(a) SOI CMOS ADC
(b) Bulk CMOS ADC
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14. EXPERIMENTAL RESULTS TID Experiment Experiment conditions
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TID Experiment
Experiment conditions
Radiation
Cobalt-60 gamma radiation source
at the room temperature
static bias state
dose rate of 50rad(Si)/s
irradiated to 500krad(Si)
Anneal
168 hours
at 100℃
Measure point
pre-radiation, 50k, 100k, 150k, 300k, 500krad(Si) and after anneal
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15. EXPERIMENTAL RESULTS TID Experiment IMECAS SOI ADC
TID tolerance > 300krad(Si)
Bulk ADC
TID tolerance <50krad(Si)
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16. EXPERIMENTAL RESULTS SEE Experiment IMECAS
DC analog input signals -0.8V, 0V and 0.8V
At room temperature
LET_Cl
17MeV•cm2/mg
flux
104/cm2•s
fluence
107/cm2
Noise window
±4LSB
Expected Digital Output
96-103， ，
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17. EXPERIMENTAL RESULTS SEE Experiment IMECAS SOI ADC SEL and SEFI
immunity
@LET = 63MeV·cm2/mg
SEU cross-section
= 17MeV·cm2/mg
= 63MeV·cm2/mg
Bulk ADC
SEL and SEFI
= 63MeV·cm2/mg
single event upset (SEU) cross-section
two order of magnitude higher than SOI ADC
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18. CONCLUSION
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In conclusion, by implementing simple RHBD approaches and taking the inherent advantage of the rad-hard SOI technology, the SOI-based ADC achieves the TID tolerance of 300krad(Si) at least, nearly one order of magnitude higher than bulk ADC, and the SEU cross-section of 9.6X10-6cm2/device at 63MeV·cm2/mg LET, lower than bulk ADC by two orders of magnitude, more suitable for harsh radiation environment applications.
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