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Global Trigger Upgrades for SLHC
Vienna, Global Trigger Group A.Taurok, C.-E. Wulz SLHC Workshop, FNAL, 19 Nov. 2008
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Global Trigger Concept for LHC and SLHC
Synchronize all Trigger Objects to arrive at the same time at the logic chip. 2008 Version: Muons: done by GMT; Calo_objects: done by PSB; TechTrig: done by PSB SLHC Version: Muons: done by GMT; Calo_objects: done by GCT; TechTrig: done by SYNC chip Tracker: done by Tracker_Trigger Send all Trigger Objects into one chip to make any correlation between them. Use a FPGA to change trigger conditions as required by physics New trigger setup: configure FPGA with new trigger conditions New parameter values for same setup: 2008 Version: Load new ET or pT thresholds and prescale values by software SLHC Version: Load all values by software Calculate physics trigger algorithms in parallel (FPGA branch) 2008 Version: 128 Algorithms limited by board layout, connectors and chip size SLHC Version: Extend to ‘nn’ Algorithms ‘Algo’ signals inside chip Chip size will be the only restriction Final OR mask for all Algorithm bits; Prescaler & Counter for each Algorithm SLHC: some other requirement ?? SLHC Version: Array of DSPs for complex physics triggers C++ code trigger program with constant latency(!) 1 optical link for each trigger object of 64 bits/40MHz 19 Nov. 2008 A. Taurok, C.-E. Wulz A. Taurok, Hephy, Vienna
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TECHNICAL TRIGGER SIGNALS
CAEN VME CONTROLLER FREE VME L1A_OUT L1A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 TCS PSB FDL GTL spare TIM GTFE GMT PC: RUN Control Detector subsystems aTTS DAQ APV-EMULATORS STATUS SIGNALS TECHNICAL TRIGGER SIGNALS 4IEG, 4EG, 4JET, 4fJET 4TAU-JET, ET*, JetNr, TOTEM CLK, ORBIT TTC - GPS-TIME S-links: DAQ, EVM (ET*=total ET, HT, MET) 8 RPC muons 4 DT muons 4 CSC muons MIP/QUIET bits LEVEL 1 GLOBAL TRIGGER 9U-VME CRATE Version 2008 128 Algo Backplane 19 Nov. 2008 A. Taurok, C.-E. Wulz
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CMS Level1 Global Trigger scheme
LHC GTL FDL Sync delay GMT COND ALGO REC 128 Algo GTL COND ALGO Final OR GCT Sync delay PSB Prescalers & Trigger Counters PSB Sync delay Technical Triggers Totem, Castor, ZDC, … SLHC COND chip Optical links FDL chip Sync delay GMT FPGA: Standard Conditions GTL nn Algo (and, or, not) GCT Sync delay COND chip Final OR - FPGA: DSPs (XC5V100T) Tracker Trigger Sync delay Tracker ‘Conditions’ Prescalers & Trigger Counters ‘Conditions’ SYNC Sync delay Totem, Castor, ZDC, … 19 Nov. 2008 A. Taurok, C.-E. Wulz
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Input to Global Trigger
Global Calorimeter Trigger (GCT): possible reduction of trigger data 4 eg, 4 isol. eg (ET, h, f) eg’s with ISOLATION bit 4 central jets, 4 forward jets (ET, h, f) jets 4 tau jets total_ET, HT apply set of thresholds in GCT and send resulting bits to FDL chip missing_ET (ET, f) HF ring ETs, etc. More than 4 objects per type: 5 or 6 (?) Simulation for SLHC Global Muon Trigger (GMT): 4 muons (pT, h, f, mip, iso, charge, quality) Tracker Trigger: Tracks/jets with h and f COND chips ‘Conditions’ calculated in Tracker Trigger FDL chip 19 Nov. 2008 A. Taurok, C.-E. Wulz
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CMS Global Trigger standard Algorithm in FPGA: example
Standard CONDITION chip ieg1 ieg4 ieg2 ieg3 ieg1 ieg4 ieg2 ieg3 Predefined VHDL code Missing Energy TEMPLATE ieg1 ieg3 Dh, Df Correlation TEMPLATE Single particle thr1, h, f window1 Single particle thr2, h, f window2 ieg2 ieg4 Single particle TEMPLATE Dh, Df Correlation ET thresholds 1,2 h, f window 1,2 Parameters Find 2 out of 4 particles fulfilling all conditions Missing Energy threshold IEG condition: ieg2wsc Missing ET condition: MET FDL chip Mask, Veto_mask Combinatorial logic: Algorithm = ieg2wsc and MET Final_OR ALGO bit (i) prescalers 19 Nov. 2008 A. Taurok, C.-E. Wulz
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CONDITION chip with DSP array, RISCs
Trigger objects (GCT, GMT, TrackerTr…) Parameters Hardwired logic* DSP Condition program Latency = # of instructions XC5VFX100T: 256 DSP48E(550MHz), 4 Ethernet MAC, 3 PCIexpress end points, 16 GTX RocketIO (6.5Gb/s) 680 IO (1.25Gb/s LVDS) Condition bit *) if DSPs are implemented in FPGA Constraints: # of Conditions # of DSPs # of instructions latency limit Keep pipeline structure Parallel or tree structures Trigger objects Trigger objects DSP DSP DSP DSP DSP DSP Latency Latency OR DSP Condition bit Condition bit Algorithm logic in FDL chip Algorithm logic in FDL chip 19 Nov. 2008 A. Taurok, C.-E. Wulz
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Global Trigger board for SLHC (‘Single board’ option)
Ethernet IP DAQ chip Ethernet IO Control CPU CMS - DAQ Event builder 2 sets of opt. rcvers Ethernet IP L1A_daq + Serial TX Control CPU L1A_daq + Serial TX RX: Serial parallel Spy_mem‘s & Ringbuffers COND_logic or DSP array nn Algo (and, or, not) LVDS Prescalers LVDS Final OR Condition bits GCT: 5 ... GMT: 2 Tracker: ~2 .. Spy_mem‘s & Ringbuffers COND chip Trigger Counters Parallel data LVDS Sync circuits LVDS Condition bits FDL chip Ethernet IP LVDS TIMING circuits LVDS CLK, BCRES, ... CLK, BCRES, .. SYNC Chip Ethernet IP 19 Nov. 2008 A. Taurok, C.-E. Wulz A. Taurok, Hephy, Vienna
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Option with Custom MTCA backplane GT logic with AMC single width module from Imperial College & LosAlamos Lab. GCT 2 copies of 7 quadruplets à 64 bits 3.2 Gbps optical links CONDITION CHIP 1+2 AMC single width (h=73.8 mm, l=181.5 mm) 12/16 FPGA 72x72 SWITCH 20 16 7 12/16 FPGA 72x72 SWITCH 20 16 TrackerTrigger 2 copies of ≤5 links à 64 bits Custom Backplane 5 1 Readout Board 512 Condition bits ALGO + FinOR (FDL) 128 Technical Trigger bits from Conversion crate 2 12/16 FPGA 72x72 SWITCH 20 16 3.2 Gbps backplane links 1 8 Readout Board Partition STATUS from 2 Big_Conversion boards 8FinalOR 1 2 12/16 FPGA 72x72 SWITCH 20 16 L1A..directly or via Big_Conversion boards to TTC system 4 1 NOT shown/defined: Global Muon Trigger Readout board with SLINK LVDS/Serial Conversion crate Readout Board 32x 8 (L1A, 5Bgo…) Central Trigger Control Readout Board as double width AMC with SLINK mezzanine board CMS_DAQ Readout data 19 Nov. 2008 A. Taurok, C.-E. Wulz
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MTCA options: 40 MHz LVDS to Serial Conversion AMC modules (Vienna)
SMALL_CONVERSION card single width, full size (w=73.8 mm, l=181.5 mm, h=28.95 mm) 8 RJ45 (59.2 x 25.5 mm) INPUT MODE OUTPUT MODE FPGA FPGA Serial link (1.6 Gbps required) Serial link (1.6 Gbps required) 32 bits 32 bits Global Trigger: 128 Technical Trigger bits 4 SMALL_CONVERSION boards (INPUT mode) Central Trigger Control: 40x4 STATUS bits 5 SMALL_CONVERSION boards (INPUT mode) 8x4 EMULATOR CONTROL signals 1 SMALL_CONVERSION boards (OUTPUT mode) 32x8 L1A+BGo signals 8 SMALL_CONVERSION boards (OUTPUT mode) Many boards!! No front panel serial links CONVERSION card double width,full size (w=148.8 mm, l=181.5 mm, h=28.95 mm) LC duplex INPUT MODE OUTPUT MODE I/O MODE Serial link (3.2 Gbps required) Serial link (3.2 Gbps required) Serial link (3.2 Gbps required) FPGA FPGA FPGA 64 bits/40MHz Synchronization, Monitoring Monitoring 64 bits/40MHz 64 bits/40MHz Global Trigger: 128 Technical Trigger bits 2 CONVERSION boards (INPUT mode) Central Trigger Control: 32x4 STATUS bits 2 CONVERSION boards (INPUT mode) 8x4x2 EMULATOR CTRL+STATUS 1 CONVERSION boards (I/O mode) 32x8 L1A+BGo signals 4 CONVERSION boards (OUTPUT mode) 9 boards Serial links (3.2 Gbps) on front panel 19 Nov. 2008 A. Taurok, C.-E. Wulz
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AFBR-57R5AEZ 4.25 Gbps, 850nm VCSEL, SFP duplex LC (Lucent)
Optical connectors MTP connector: 18 mm x 40(space on board); 11.2 mm from board edge to front side, h= 11mm without heatsink SFP+ connector: transcvr, w=13,7, L=56.5, h=8.6mm LC connector: w=4.52 mm, h=5.7 Duplex LC: 6.25mm middle-middle~14 mm Panduit MTP module: FC Y or FCXO-… 24 single mode fibers9/125, 2mtp to 12 duplex LC, w = 88.9 mm. L=144.2, h=35.3 Avago optical transcvr: duplex LC with 6.25mm middle-middle; w= 14.9 or 13.6; h= 12.4mm double width AMC boards (h=148.8 mm, l=181.5 mm) Conversion board: AFBR-57R5AEZ Gbps, 850nm VCSEL, SFP duplex LC (Lucent) 20x20mm FPGA 35x35mm 19 Nov. 2008 A. Taurok, C.-E. Wulz
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Option with Standard MTCA backplane: Crate examples
Example: Single width shelf (Schroff/Pentair) Example: Double width shelf (Schroff/Pentair) Example: single width Cube (Elma) Mechanical problems Ruggedized crates from other suppliers: vibration, shock isolation 19 Nov. 2008 A. Taurok, C.-E. Wulz Single width shelf
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Option with Standard MTCA backplane: Example of standard MCH (MTCA carrier hub) module
NAT-MCH ( Central management and data switching entity Fast Ethernet CPU management Giga-Ethernet uplink to backplane CPU: carrier-,shelf-, system manager Fabric D-G: Serial Rapid I/O (PICMG AMC.4) Fabric A: Gigabit Ethernet Fabric B: Serial Attached SCSI Clock mezzanine NAT-MCN Clock mezzanine Tundra TSi578 (Tundra Web page) RapidIO 1.25, 2.5, and Gbits/s per port 19 Nov. 2008 A. Taurok, C.-E. Wulz
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Double width TCA board for GT
double width,full size (w=148.8 mm, l=181.5 mm, h=28.95 mm) 181.5 mm BLUE LINES: ‘nn’ Serial links between FPGA <1 Gbps ~ 16 bits à 40 MHz ~32 parallel LVDS 40/80 MHz 3.2 Gbps RJ45 Port4(8) FPGA ~35x35mm MTP 12 REC ~18x40mm Port5(9) FPGA MTP 12 REC 3.2 Gbps Port links between Boards Speed depends on MCHUB 3.2 Gbps 1 Gbps 148.8 mm Port6(10) MTP 12 REC FPGA RJ45 Optional Ethernet Port7(11) MTP 4 REC, 4 TX CTRL FPGA 3.2 Gbps Port0,1 MTP 4 REC, 4 TX POWER JTAG CLOCK 19 Nov. 2008 A. Taurok, C.-E. Wulz
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Option with Standard MTCA backplane: GMT+GT crate with double width AMC modules (Vienna)
3.2 Gbps MCH1 fat pipe (Readout) GMT Global Muon Trigger CSC+fRPC 8 muons Port4(8) 4 12 IN+LFF FPGA Standard Backplane Port5(9) 8 AU FPGA 4+4+2 GCT 504 M+Q bits 12 4 12 IN+LFB FPGA Port6(10) DT+bRPC 8 muons double width AMC boards (h=148.8 mm, l=181.5 mm) Port7(11) 1 Readout board SRT+ CTRL 4 8r8tx to GTL 4 muons port0,1 MTP connector: 12 fibers rec/tr 18 mm x 40 mm GCT 2 copies of 7 quadruplets á 64 bits ALGO(GTL) + FinOR (FDL) 2 Port4(8) 12 COND1 FPGA 7 Port5(9) FDL FPGA 12 TrackerTrigger 2 copies of ~2 links à 64 bits 2 2 12 Port6(10) COND2 FPGA spare Port7(11) 1 CTRL FPGA Readout board 8r8tx 8FinalOR Central Trigger Control port0,1 1 128 Technical Trigger bits parallel LVDS 1 2 CONVERSION cards MCH2 fat pipe (Trigger data) Readout Board CMS_DAQ SLINK 19 Nov. 2008 A. Taurok, C.-E. Wulz
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Option with Standard MTCA backplane: Central Trigger Control Crate
MCH1 fat pipe (Monitoring) double width AMC boards (h=148.8 mm, l=181.5 mm) Central Trigger Control & Readout Port4(8) Standard Backplane 12 xxx FPGA Port5(9) xxx FPGA 4+4+2 12 1 8FinalOR 12 TCS FPGA Port6(10) 1 2 Port7(11) Readout board TCSM+ CTRL 1 8r8tx 4 port0,1 32x 8 (L1A, 5Bgo…) Readout Board with SLINK mezzanine board to be defined. 2 Partition STATUS Parallel LVDS CONVERSION card input mode L1A, BGo… to TTC 32 x 8 signals CONVERSION card output mode EMULATORs 8x 4 bits status bits 8x 4 bits control signals CONVERSION card I/O mode Control data: Bgo, L1A, Resync, Bcres… MCH2 fat pipe (Control data) 32x 8 (L1A, 5Bgo…) Central Trigger Control 19 Nov. 2008 A. Taurok, C.-E. Wulz
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Conclusions Basic design idea for an upgraded Global Trigger exists.
First idea was a VME implementation, using DSP’s. Implementation in MTCA technology now seems feasible. Double width AMC boards for GT and TCS logic is preferred. Standard and custom MTCA backplane options are considered. 19 Nov. 2008 A. Taurok, C.-E. Wulz
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