1. The Data Handling Hybrid
TUM Physics Department E18
I.Konorov

2. DEPFET meeting I.Konorov
Overview
DHH design
SODA -Time Distribution system for PANDA
Specification and Requirements
Project schedule
8-th March 2010
DEPFET meeting I.Konorov

3. DEPFET meeting I.Konorov
DHH functionality
Power supplies
Slow control: voltages, currents, temperature, switching ON/OFF ladder power supply(?)
Distribution of TRIGGER, RESET(?) … signals
Generation of CLOCK signals
JTAG interface
DAQ functionality
Receiving 4 data streams with up to 1Gb/s
Data buffering
Subevent builder
Data transfer to DAQ via high speed optical serial link
8-th March 2010
DEPFET meeting I.Konorov

4. DEPFET meeting I.Konorov
DHH design
to DAQ
to DHH Controller
8-th March 2010
DEPFET meeting I.Konorov

5. DHH system architecture
DHH Controller
FPGA
Trigger
Clock
Belle
DAQ
Reset
Ready
PCIe
USB
VME
JTAG
8-th March 2010
DEPFET meeting I.Konorov

6. DEPFET meeting I.Konorov
SODA serial interface
125 MHz or 1.25 Gb/s now, in future may go up to 2.5Gb/s
Bidirectional link :
Controller -> Receivers full bandwidth of 125 MB/s
Broadcast synchronous commands with fixed latency, 32 bit long:
RESET, Start/Stop data taking, Start/End of burst
Asynchronous commands , 32 bit long
Scanning connected modules
Control
Packets up to 1kB
Receivers -> Controller
Time sharing principle, similar to common bus
Only one receiver can send data at a time
Controller schedules Receivers access
Switching from one receiver to another takes 400 ns
Laser OFF - Laser On – Relock SERDES to new receiver
Heartbeat packet
Status packet
CNTR
RCV
8-th March 2010
DEPFET meeting I.Konorov

7. SODA system components
1:8
1:16
Passive optical splitters
Passive optical splitters 1:8, 1:16, 1:32
Insertion losses 9.5dBm, 12.5dBm, 16dBm
Receiver
SFP cage
Lattice ECP2M-35 FPGA, 4xSERDES
TI TLK1221 – fast relock chip
IO interface
LVDS clock
LVDS reset
JTAG, slave and master
High Speed serial interface
8-th March 2010
DEPFET meeting I.Konorov

8. DEPFET meeting I.Konorov
Test setup
Lattice PCI-e evaluation card
Optical splitter 1:8
2x SODA receivers mounted on evaluation cards
Reference Clock vs Recovered Rx Clock
10ps/div
RMS 15ps
8-th March 2010
DEPFET meeting I.Konorov

9. DEPFET meeting I.Konorov
DHH Requirements
Functionality
LV power supplies
Clock frequencies
Slow control – JTAG and monitoring
Data rate
Reliability requirements
Form factor and position
Connectors
Type
Pin assignment
Interface protocols
8-th March 2010
DEPFET meeting I.Konorov

10. Time lines (preliminary)
Requirements and specification
Prototype development
Test, debugging, final specification
Final prototype
Final production
8-th March 2010
DEPFET meeting I.Konorov