1. Implementing Combinational
ECE 448
Lab 2
Implementing Combinational
and Sequential Logic
in VHDL
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University

2. Agenda for today Part 1: Introduction to Lab 2
Implementing Combinational and Sequential
Logic in VHDL
Part 2: Hands-on Session:
Simulation Using Aldec Active-HDL
Part 3: Lab Exercise 1

3. Part 1 Introduction to Lab 2
ECE 448 – FPGA and ASIC Design with VHDL

4. Discussion of the Diagram, Requirements, and Hints

5. Interface : Combinational Logic
Interface of an 8-bit ALU

6. Ports Name Mode Width Meaning A IN 8 Input A B Input B Cin 1 Carry In
OPCODE 4
Operation Code X
OUT
Output or Least Significant Byte of Output Y
Most Significant Byte of Output or Zero Z
Zero Flag
Cout
Carry out Flag V
Overflow Flag
F_active
Logical OR of Z, Cout and V
X_bin_pal
Flag set to high when the output X is a binary palindromic number (numbers that remain the same when binary digits are reversed)
X_prime
Flag set to high when the output X is a prime number N
Flag set to high when the output X is a negative number

7. Instruction Set OPCODE OPERATION FORMULA Z Cout V X_bin_pal X_prime N
0000
AND
X = A AND B ↕ 
0001 OR
X = A OR B
0010
XOR
X = A XOR B
0011
XNOR
X = A XNOR B
0100
Unsigned Addition
(Cout:X) = A + B
0101
Signed Addition
X = A + B
0110
Unsigned Addition with Carry
(Cout:X) = A + B + Cin
0111
Signed Multiplication
(Y:X) = A * B
1000
Unsigned Multiplication
1001
Unsigned Subtraction
X = A - B
1010
Rotation Left
X = A <<< 1
1011
Rotation Left with Carry
(Cout:X) = (Cin:A) <<< 1
1100
Logic Shift Right
X = A >> 1
1101
Arithmetic Shift Right
1110
Logic Shift Left
X = A << 1
1111
BCD to Binary Conversion
(Y:X) = BCD2BIN(B:A)

8. Interface : Sequential Logic
Interface of an ALU_SEQ

9. Ports Name Mode Width Meaning CLK IN 1 System clock RESET
Reset active high I 8
Value of an operand A or B
LOAD
Loading value at input I to one of the internal registers holding A or B
(control signal active for one clock period;
the action takes place at the rising edge of the clock)
SEL_IN
0: loading register A
1: loading register B OP 4
Operation mode
RUN
Writing the result to registers holding X0, X1, Y0, and Y1 (control signal active for one clock period; the action takes place at the rising edge of the clock)

10. Logical OR of Z, Cout and V. X_bin_pal
Name
Mode
Width
Meaning
SEL_OUT IN 1
0: R = X
1: R = Y R
OUT 8
Digit of a result Z
Zero flag.
Cout
Carry out flag. V
Overflow flag.
F_active
Logical OR of Z, Cout and V.
X_bin_pal
Flag set to high when the output X is a binary palindromic number (numbers that remain the same when binary digits are reversed)
X_prime
Flag set to high when the output X is a prime number N
Flag set to high when the output X is a negative number

11. Sequential Logic: Block Diagram
of the Datapath

12. Bonus Task
OPCODE
OPERATION
FORMULA Z
Cout V
X_bin_pal
X_prime N
1010
Variable Rotation Left
X = A <<< B ↕ 
1011
Variable Rotation Left with Carry
(Cout:X) = (Cin:A) <<< B
1100
Variable Logic Shift Right
X = A >> B
1101
Variable Arithmetic Shift Right with Rounding
X = (A >> B) + A(B-1)
1110
Variable Logic Shift Left
X = A << B
A <<< B = rotation of A left by the number of positions given by a value of B.
A << B = shift of A left by the number of positions given by a value of B.
A >> B = shift of A right by the number of positions given by a value of B.
X = (A >> B) + A(B-1) = An arithmetic shift by the number of positions given by B followed by a rounding operation, which consists of adding the value of the B-1st bit of A to the result of the shift.

13. Simulation Using Aldec Active-HDL
Part 2
Hands-on Session:
Simulation Using Aldec Active-HDL
ECE 448 – FPGA and ASIC Design with VHDL

14. based on the MLU example
Hands-on Session
based on the MLU example
with simple testbench

15. Part 3
Lab Exercise 1
ECE 448 – FPGA and ASIC Design with VHDL

16. Interface : ALU

17. ALU: Block Diagram