1. Faults in Circuits and Fault Diagnosis
Fault table
Test experiment
Fault
modeling F 1 2 3 4 5 6 7 T
How many rows
and columns should be
in the Fault Table? 1 1 T 1 1 1 6
Fault F
located 5
Testing
Fault diagnosis
Fault simulation
Test generation

2. Boolean derivatives Y = F(x) = F(x1, x2, … , xn) Boolean function:
Boolean partial derivative:

3. Boolean Derivatives Useful properties of Boolean derivatives:
These properties allow to simplify the Boolean differential equation
to be solved for generating test pattern for a fault at xi
If F(x) is independent of xi
Näide:

4. Calculation of Boolean Derivatives
Calculation of the Boolean derivative:
Given:

5. Derivatives for complex functions
Boolean derivative for a complex function:
Example:
Additional condition:

6. Boolean vector derivatives
If multiple faults take place independent of xi
Example:

7. Boolean vector derivatives
Calculation of the vector derivatives by Carnaugh maps: x2 x2 x2 1 1 1 1 1 1  = 1 1 x3 x3 1 1 1 1 1 1 1 1 x3 x1 x1 x1 1 1 1 1 1 1 1 1 x4 x4 x4

8. Boolean vector derivatives
Interpretation of three solutions:
Two paths activated 1
Single path activated 1

9. BDDs and Testing of Logic Circuits1
Path
activation
Fault
Stuck - at
Correct
signal
Error x 2 3 = 4 5 6 7 y F ( X ) x 1 2 y 3 4 5 6 7
By the BDD for F(X) we can generate test patterns only for testing inputs
How about testing the internal nodes
of the circuit?  SSBDD
The tasks on BDDs:
Pattern simulation (analysis)
Pattern generation (synthesis)

10. Test Generation with SSBDDs
& 1 x1 x2 x3 x4 y
Test generation for:
x11
x21
x12
x31
x13
x22
x32
x110
10
x11 y
x21
x12
x31 x4
x13
x22
x32 1
10
Structural BDD: x1 y x2 x4 x3
Functional BDD: 1
10
x1 x2 x3 x4 y
Test pattern:
1 0

11. Functional Synthesis of BDDs
Shannon’s Expansion Theorem: xk y
Using the Theorem
for BDD synthesis: 1 x1 x2 1 x3 x4 x3 x4 1

12. Functional Synthesis of BDDs
Shannon’s Expansion Theorem: x1 x2 1 x3 x4 x1 x3 x2 1 x4

13. BDDs for Logic Gates Elementary BDDs: SSBDD synthesis: OR AND NORx1 x2 x3 y
&
AND 1 1 x2 x3 y x1 OR 1 1 x1 x2 x3 y
NOR
Given circuit:
& 1 x1 x2 x3
x21
x22 y a b
SSBDD synthesis:
SSBDDs for a given circuit are built by superposition of BDDs for gates

14. Synthesis of SSBDD for a Circuit
Superposition of BDDs:
Given circuit: a b y x1 a
x21 1 x2 y
& b
x22 x3
x22 a y
x22 x3 b 1 x3 b
Structurally Synthesized BDD:
Compare to a x1
x21 x3 y
x22 x1
x21 a
Superposition of Boolean functions:

15. SSBDD for the full circuit:
Synthesis of SSBDDs by Superposition of BDDs
Example: Superposition of two graphs – SSBDD x3 is embedded into the graph y instead of the node x3
SSBDDs for FFRs:
Network of two sub-circuits: x 1 y 5 2 4 6 8 9 7
SSBDD for the full circuit: x 1 y 3 5 2 4 6 8 9 7 y
FFR
FFR x3

16. HLDDs and Faults RTL-statement: K: (If T,C) RD  F(RS1,RS2,…RSm),  N
Terminal nodes
RTL-statement faults:
data storage,
data transfer,
data manipulation faults
Nonterminal nodes
RTL-statement faults:
label,
timing condition,
logical condition, register decoding,
operation decoding,
control faults
Control path
Data path

17. Decision Diagrams for Microprocessors
Instruction
set: I R 3 A
OUT 4
DD-model of the
microprocessor: A I IN
1,6
2,3,4,5
A + R 7
A  R 8
A  R 9
 A 10
I1: MVI A,D A  IN
I2: MOV R,A R  A
I3: MOV M,R OUT  R
I4: MOV M,A OUT  IA
I5: MOV R,M R  IN
I6: MOV A,M A  IN
I7: ADD R A  A + R
I8: ORA R A  A  R
I9: ANA R A  A  R
I10: CMA A,D A   A I A 2 R IN 5
1,3,4,6-10

18. Synthesis of Functional HLDDs
Results of cycle based symbolic simulation:
Data Flow Diagram/FSMD
Constraints
Assignment statements q xA xB xC
A = B + C; q = 1 1
A = A + 1; q = 4
B = B + C; q = 2 2
C = A + B; q = 5
C = C; q = 3 3
A = C + B; q = 5 4
B = B
A = A + B + C; q = 5
q = 5
C = C; q = 5
q = 0
Begin
q = 1
A = B + C x 1 A
q = 4
q = 2
A = 
A + 1
B = B + C x 1 x 1 A B
q = 3
B =  B
C =  C
C =  C x 1 x 1 C C
A = A + 
B + C
C = A + B
A = 
C + B
q = 5
END

19. Extraction of the behaviour for A: Results of symbolic simulation:
Synthesis of HLDDs
Extraction of the behaviour for A:
Results of symbolic simulation: q xA xB xC A
B + C 1
A + 1 3
C + B 4
A + B + C
Constraints
Assignment statements q xA xB xC
A = B + C; q = 1 1
A = A + 1; q = 4
B = B + C; q = 2 2
C = A + B; q = 5
C = C; q = 3 3
A = C + B; q = 5 4
B = B
A = A + B + C; q = 5
q = 5
C = C; q = 5
A = f (q, A, B, C, xA, xC) =
= (q=0)(B+C) 
(q=1)(xA=0) (A + 1) 
(q=3)(xC=1)( C+B) 
(q=4)(xA=0)(xC=0)(A+ B + C + 1)
Predicate equation for A:

20. Decision diagram for A:
Synthesis of HLDDs
Decision diagram for A:
Extraction of the behaviour for A: q xA xB xC A
B + C 1
A + 1 3
C + B 4
A + B + C
Predicate equation for A:
A = (q=0)(B+C)  (q=1)(xA=0) (A + 1) 
(q=3)(xC=1)( C+B) 
(q=4)(xA=0)(xC=0)(A+ B + C + 1)
Synthesis method: similar to Shannon’s expansion theorem:

21. Functional HLDDs Data Flow Diagram Decision Diagrams
Begin
A = B + C x A
A = 
A + 1
B = B + C
B = B
C = C
A = A +
B + C
C = A + B
C + B
END 1 s 2 3 4 5
Register variables
State variable

22. Structural and Functional Fault Modelingx1 a
Classification of fault models x2
x21
& y 1
Fault models are: explicit and implicit
explicit faults may be enumerated
implicit faults are given by some characterizing properties
Fault models are: structural and functional:
structural faults are related to structural models, they modify interconnections between components
functional faults are related to functional models, they modify functions of components
x22 x3
& b
Structural faults:
- line a is broken
- short between x2 and x3
Functional fault:
Instead of

23. Structural Logic Level Fault Modeling
Stuck-at fault model:
Why logic fault models?
complexity of simulation reduces (many physical faults may be modeled by the same logic fault)
one logic fault model is applicable to many technologies
logic fault tests may be used for physical faults whose effect is not completely understood
they give a possibility to move from the lower physical level to the higher logic level
Stuck-at-0
Broken line
Bridge to ground x1 x1 x2 1 x2 1 0V
Stuck-at-1
& x2 x1
Broken line 1
Bridge to Power Supply
Vdd

24. Stuck-at Faults and their Properties
Fault equivalence and fault dominance:
A B C D Fault class
A/0, B/0, C/0, D/ Equivalence class
A/1, D/0
B/1, D/ Dominance classes
C/1, D/0 A
& B D C
&
Fault collapsing:
 1 1
 0
Equivalence
& 1
 0
 1
Dominance
Equivalence 1
 1
Dominance

25. Resistive bridge fault Multiple faulty signal
Extended Fault Models
Extensions of the parallel critical path tracing for two large general fault classes for modeling physical defects:
Multiple fault
Resistive bridge fault 1
Defect
SAF
X-fault
Byzantine fault
Bridges
Stuck-opens
Multiple faulty signal
Conditional fault
Pattern fault
Constrained SAF
Single faulty signal

26. Extending of Fault Models: Bridging
Wired AND/OR model x2
x’2
W-AND:
Fault-free
W-AND
W-OR x1 x2
x’1
x’2 1 x1
x’1
& x2
x’2 1 x1 x2
x’1
x’2
W-OR:

27. Testing of Bridging Fault Modelsx1
x’1
Wired AND model x2
x’2
W-AND: x1
x’1
&
&
X1 = 1
X3 = 1  0
y1 = 1  0
X2 = 1
0  1
X4 = 0
X5 = 1
y2 = 1 x2
x’2

28. Testing of Bridging Fault Modelsx1
x’1
Wired OR model x2
x’2
W-OR: x1
x’1 1
&
X1 = 1
X4 = 0  1
y2 = 1  0
X2 = 1
X3= 1
X5 = 1
y1 = 1 x2
x’2

29. Delay Fault Models Fault models:
Delay faults are tested by test pattern pairs: ) First pattern initializes circuit
2) Second pattern sensitizes the fault x1 11 B 00
&
001 D y A
& x2 01 C 10
& x3
&
110 11
Clock
Fault models:
Gate delay fault (delay fault is lumped at a single gate, quantitative model)
Transition fault (qualitative model, gross delay fault model, independent of the activated path)
Path delay fault (sum of the delays of gates along a given path)
Line delay fault (is propagated through the longest senzitizable path)
Segment delay fault (tradeoff between the transition and the path delay fault models)

30. Register Level Fault Models
RTL statement:
K: (If T,C) RD  F(RS1, RS2, … RSm),  N
Components (variables)
of the statement:
RT level faults:
K  K’ - label faults
T  T’ - timing faults
C  C’ - logical condition faults
RD  RD - register decoding faults
RS  RS - data storage faults
F  F’ - operation decoding faults
 - data transfer faults
 N - control faults
(F)  (F)’ - data manipulation faults
K - label
T - timing condition
C - logical condition
RD - destination register
RS - source register
F - operation (microoperation)
 - data transfer
 N - jump to the next statement

31. Universal Functional Fault Model
Exhaustive combinational fault model:
- exhaustive test patterns
- pseudoexhaustive test
patterns
- exhaustive output line
oriented test patterns
- exhaustive module

32. HLDDs and Faults RTL-statement: K: (If T,C) RD  F(RS1,RS2,…RSm),  N
Terminal nodes
RTL-statement faults:
data storage,
data transfer,
data manipulation faults
Nonterminal nodes
RTL-statement faults:
label,
timing condition,
logical condition, register decoding,
operation decoding,
control faults
Control path
Data path

33. From Trad. MP Fault Model to HLDD Faults
Each path in a DD represents a working mode of the system
The faults having effect on the behaviour can be associated with nodes along the path
D1:  node output is always activated (SAF-1)
D2:   node output is broken (SAF-0)
D3:  instead of the given output another output set is activated
Instead of the 14 fault classes,the HLDD based fault model includes only 3 fault classes

34. Gate-Level Test Generation
Single path fault propagation:
Fault sensitisation:
x7,1= D
Fault propagation:
x2 = 1, x1 = 1, b = 1, c = 1
Line justification:
x7= D = 0: x3 = 1, x4 = 1
b = 1: (already justified)
c = 1: (already justified) 1 1 1
Macro 1 1 d 2 a
& D 71
& D D 1
& 3 e
& 7 72 1
& b 4 1 D y 5
& D 73
& c 1 6
Test pattern
Symbolic fault modeling:
D = if fault is missing
D = if fault is present

35. Testing of Inputs 1 a1 a b b 1 1 1 a2 y No test for  0 a b y a1 a2
& b 1 1 1 a2 y
& 1
No test for  0
& 1 a b y a1 a2
No test for  1 a1 a b
& b 1 a2 y
& 1
Test for  1 1

36. Testing of Inputs 1 a1 a 1 b
& b 1
No test for  0 a2 1 c
& 1 y c a3
&

37. Test Generation with BD and BDDy x1 x2
BD: x3 x2 x4 x1 x4 x5 1 x2 x6
Test pattern: x1 x2 x1 x2 x3 x4 x5 x6 y 1 - D

38. BDDs and Test Generation
& 1 x1 x2 x3 x4 y
Test generation for:
x11
x21
x12
x31
x13
x22
x32
x110
10
Test generation
for:
x10
x11 y
x21
x12
x31 x4
x13
x22
x32 1
10
Structural BDD: x1 y x2 x4 x3
Functional BDD: 1
10
x1 x2 x3 x4 y
Test pattern:
1 0
ALGORITHM:
Begin TG with Functional BDD
Simulate the test on Structural BDD
Update the test on Structural BDD

39. Example: Test Generation with SSBDDs
Testing Stuck-at-1 faults on paths:
x11 y
x21
x12
x31 x4
x13
x22
x32 1
x11 x1
x21 x2
&
x12
x31 x3 y
& 1 x4
Test pattern:
&
x13
&
x1 x2 x3 x4 y
x22
x32
Tested faults: x121, x221
Not tested: x111

40. Hierarchical Test Generation
Component under test
Component
level test: D1 D2 D 1 D2 x1
&
& x2 1 y D1 x3
& D1 D 1
Network level test: x4
& 1 1 x5 D x1 x2 x3 x4 x5 y D2 D1 1 D D2
&
&
Symbolic test: contains 3 patterns 1

41. Fast and Simple Test Generation
Test generation by using disjunctive normal forms
& 1 x1 x2 x3 x4 y
x11
x21
x12
x31
x13
x22
x32

42. Pseudoexhaustive Test Optimization
Output function verification (partial parallelity)
0011
0101 F1
- 0 F5 1 x1
F1(x1, x2)
F2(x1, x3) 01 10 x2
F3(x2, x3) F3 x3
F4(x2, x4)
0101 F2
F5(x1, x4)
00 1 F4 1 x4
F6(x3, x4)
Exhaustive testing - 16
Pseudo-exhaustive, full parallel – 4 (not possible)
Pseudo-exhaustive, partially parallel - 6

43. Multiple Fault Testing
Multiple stuck-fault (MSF) model is an extension of the single stuck- fault (SSF) where several lines can be simultaneously stuck
If n - is the number of possible SSF sites, there are 2n possible SSFs, but there are 3n -1 possible MSFs
If we assume that the multiplicity of faults is no greater than k , then the number of possible MSFs is
– number of sets of i lines, i - number of faults on the set
The number of multiple faults is very big. However, their consideration is needed because of possible fault masking
0,1,x
Wire a
0,1,x
Wire b

44. Multiple Fault Testing
The problem arised: Fault Masking
Multiple fault F may be not detected by a complete test T for single faults
because of circular masking among the faults in F
Test pattern set
T = {1111, 0111, 1110, 1001, 1010, 0101} detects every single fault 1 a
1/0
& b 1
&
0/1
The only test for detecting
b  1 or c  1 is 1001
0/1
&
0/1
0/1
& 1 c 1
&
However, b  1 masks c  1
and c  1 masks b  1 d
1/0

45. Test Pairs for Multiple Fault Testing
Testing of multiple faults by pairs of patterns
Tested path for b  1/0
To test a path
under any multiple faults,
two pattern test is needed 11 a 00 01
&
No error b
11/11
&
b 1
00/11
The lower path from b is under test
A pair of patterns is applied on b
There is a masking fault c  1
01/00
&
c 1 01 00
&
Error 11 c
10/11
& 11 d
11/00
1st pattern: fault b  1 is masked
Either the fault on the path is detected or the masking fault is detected
2nd pattern: fault c  1 is detected
The secret: 1st pattern tests b
2nd pattern tests c

46. Test Generation for Digital Systems
High-level test generation with DDs: Conformity test
Decision Diagram
Multiple paths activation in a single DD
Control function y3 is tested R 2 y # 4
Data path 1 R R 2 M 3 e + 1 a * b IN c d y 4 2 2 y y 3 1 R + R 1 2 1 IN + R 2 1 IN 2 R 1 3 y 2 R * R 1 2 1
Control: For D = 0,1,2,3: y1 y2 y3 y4 = 00D2
Data: Solution of R1+ R1  IN  R1  R1* R1
IN* R
Test program: 2

47. Test Generation for Digital Systems
High-level test generation with DDs: Scanning test
Decision Diagram
Single path activation in a single DD
Data function R1* R2 is tested R 2 y # 4
Data path 1 R R 2 M 3 e + 1 a * b IN c d y 4 2 2 y y 3 1 R + R 1 2 1 IN + R 2 1 IN 2 R 1 3 y 2 R * R 1 2 1
Control: y1 y2 y3 y4 = 0032
Data: For all specified pairs of (R1, R2)
IN* R
Test program: 2

48. Decision Diagrams for Microprocessors
Instruction
set: I R 3 A
OUT 4
DD-model of the
microprocessor: A I IN
1,6
2,3,4,5
A + R 7
A  R 8
A  R 9
 A 10
I1: MVI A,D A  IN
I2: MOV R,A R  A
I3: MOV M,R OUT  R
I4: MOV M,A OUT  IA
I5: MOV R,M R  IN
I6: MOV A,M A  IN
I7: ADD R A  A + R
I8: ORA R A  A  R
I9: ANA R A  A  R
I10: CMA A,D A   A I A 2 R IN 5
1,3,4,6-10

49. Decision Diagrams for Microprocessors
High-Level DD-based structure of the microprocessor (example):
DD-model of the
microprocessor:
1,6 IN A I IN R 3
2,3,4,5
OUT I R A 4 I 7
OUT
A + R A 8 2
A  R
A + R R I A 9 A
A  R 5 IN 10
 A
1,3,4,6-10 R

50. Test Program Synthesis for Microprocessors
Scanning test program for adder:
Instruction sequence T = I5 (R)I1 (A)I7 I4
for all needed pairs of (A,R)
Test program:
For j=1,n
Begin
I5: Load R = IN(j1)
I1: Load A = IN(j2)
I7: ADD A = A + R
I4: Read A
End
IN(j1)
IN(j2) A
Test data Test results I4
OUT I7 A I1 A R
IN(2) I5 R
IN(1)
Time: t
t - 1
t - 2
t - 3
Observation Test Load

51. Parallel Fault & Test Pattern Simulation
Parallel patterns
Parallel faults
Fault-free circuit:
Three test patterns
Computer word
001 x1 z
001
Fault-free
&
011 x2 1 y
101 x3
010
Stuck-at-1
Inserted faults
Stuck-at-0
Faulty circuit:
Detected error
Inserted
stuck-at-1 fault
000 x1 z
0 1 0
&
010 x2 1 y
111 x3
001
000 x1 z
111
&
111
Detected error x2 1 y
101 x3
010

52. Critical Path Tracing & & 1 1 & & 1 & 1 & Problems: 1 1 1 b 1 1 2 1 1
1/0 1 1 y y
1/0 3
&
& 1 c 4 1 1 5 a
The critical path is not continuous y 1 2 1
& 1 1 1
1/0 y 3 4
& 1 5
The critical path breaks on the fan-out

53. Deductive Fault Simulation with BDs
Macro-level fault propagation:
Fault list calculated: 1 1 b
& 1
Ly = (L1  L2) - (L3  (L4  L5)) 2 1 1 1 y 3
&
 Lk A B c 4 1 5 a
Solving Boolean differential equation: A B A B

54. Fault Analysis with SSBDDs
Algorithm:
Determine the activated path to find the fault candidates
Analyze the detectability of the each candidate fault (each node represents a subset of real faults)
& 1 x1 x2 x3 x4 y
x11
x21
x12
x31
x13
x22
x32
x11 y
x21
x12
x31 x4
x13
x22
x32 1

55. Fault Simulation with Boolean Derivatives
Simulation approaches:
Single fault simulation
Parallel fault simulation for a subset of test patterns (by extending bit-operations to operations with computer words)
Iterative fault simulation for subsets of faults (by creating transitive closures – deductive simulation and critical path tracing)
Parallel fault simulation for both, patterns and faults
1011 x1
& x2
1110
1011
1001 1 y x3
Detected faults vector:
T1: No faults detected
T2: x1  1 detected
T3: x1  0 detected
T4: No faults detected

56. Parallel Critical Path Tracing
Handling of fanout points:
Fault simulation
Boolean differential calculus
1011 x1
& x2
1110
1011
1001 1 y x3 x1 F x2 x y xk
Detected faults vector:
T1: No faults detected
T2: x1  1 detected
T3: x1  0 detected
T4: No faults detected

57. Faults in Circuits and Fault Diagnosis
Fault table
Test experiment
Fault
modeling F 1 2 3 4 5 6 7 T
How many rows
and columns should be
in the Fault Table? 1 1 T 1 1 1 6
Fault F
located 5
Testing
Fault diagnosis
Fault simulation
Test generation

58. Sequential Fault Diagnosis
Sequential fault diagnosis by Edge-Pin Testing
Diagnostic tree:
Two faults F1,F4 remain indistinguishable
Not all test patterns used in the fault table are needed
Different faults need for identifying test sequences with different lengths
The shortest test contains two patterns,
the longest four patterns

59. Sequential Fault Diagnosis
Guided-probe testing at the gate level
Searh tree:
Faulty circuit

60. Optimized Critical Path Tracing with BDDs
Property 2:
If a test vector X
activates in SSBDD a 0-path (1-path)
which travers a subset of nodes M,
then only 0-nodes
(1-nodes) have to be considered as fault candidates
Fault diagnosis / Fault simulation: y y
Fault diagnosis and fault simulation
can be speed-up
by using Property 2
Speeding-up simulation:
M = {1,2,3,4,6,7}
M* = {1,6,7} – by Property 2
M** = {6,7} – by Property 1
Only 6 and 7 have to be considered

61. Improving Diagnostic Resolution
Generating tests to distinguish faults
How to activate a fault
without activating another one?
Method:
Both faults influence the same output of the circuit
One of them should be blocked
Two possibilities:
A test pattern 0100 activates the fault F2. F1 is not activated: the line x3,2 has the same value as it would have if F1 were present
A test pattern 0110 activates the fault F2. F1 is now activated at his site but not propagated through the AND gate x
5,1
5,2 2 3 4
3,1
3,2 5 6 7 8 1
&
0/1
F1: x3,2  F2: x5,2  1

62. Improving Diagnostic Resolution
Generating tests to distinguish faults
How to activate a fault
without activating another one?
Method:
Both of the faults may influence only the same output
Both of the faults are activated to the same OR gate, none of them is blocked
However, the faults produce different values at the inputs of the gate, they are distinguished
if x8 = 0, F1 is present
otherwise, if x8 = 1 (OK value)
either F2 is present
or none of the faults are present
F1: x3,1  1 1 x 1 x 1 7 x x x 2 5
5,1 1 x
5,2 x x
3,1 1 x 3 x 8
3,2 x 6
& x 4 1
F2: x3,2  1

63. Boolean Differentials and Fault Diagnosis
dx fault variable, dx  (0,1)
dx = 1, if the value of x has changed because of a fault
Partial Boolean differential (for fault simulation):
Full Boolean differential (for fault diagnosis):

64. Boolean Differentials and Fault Diagnosis
Diagnostic experiment:
Substitution of values:
x1 = 0
x2 = 1
x3 = 1
dy = 0
Test pattern
- Correct reaction
Adjusting for SAF faults:
Partial diagnosis:

65. Boolean Differentials and Fault Diagnosis
1) Correct output signal:
x1 = 0
x2 = 0
x3 = 0
dy = 1
Two diagnostic experiments:
x1 = 0
x2 = 1
x3 = 1
dy = 0
2) Erroneous output signal:
Diagnosis from two experiments:

66. Boolean Differentials and Fault Diagnosis
Diagnosis from two experiments:
Rule:
= 0
Rule:
Final diagnosis:
The line x3 works correctly
There is a fault:
The fault is missing