1. ECE 353 Introduction to Microprocessor Systems
Week 7
Michael J. Schulte

2. Topics Clock and reset generation. Bus timing.
Bus signal demultiplexing.
System buffering
Determining suitability of logic family interconnections.

3. System Diagram

4. 80C188EB Package Mulitplexed vs configurable pins Key signals
mulitplexed address/data - AD(7:0)
non-multiplexed address - A(15:8)
address valid only during T1 – A(19:16)
status lines valid from phase 2 of preceding T state (T4 or TI) until end of T3

5. Clock and Reset Clock Generation Reset Internal Oscillator
External Oscillator
Processor Clock
Reset
Cold-start vs. warm-start
RC reset circuit
Microprocessor Supervisors
MAX807

6. Bus Cycles Basic Read Cycle Sequence at Bus Level
Diagram
Basic Write Cycle Sequence at Bus Level
States and Phases
Bus Cycle State Diagram
Types of Bus Cycles
S2:0 indicate the type of bus cycle in progress.

7. Bus Cycles 80C188EB Bus Cycle Timing
Read Cycle
Write Cycle
Exercise: What type(s) of bus cycles are run? What address and data during each?
001A BA mov dx, 1000h
001D C mov [bx], 1234h
A mov al, [bx]
0023 EE out dx, al
0024 ED in ax, dx

8. Demultiplexing Multiplexed Signal Timing Demultiplexing Strategies
Bus signal phases
Demultiplexing Strategies
Remote Demultiplexing
Local Demultiplexing
Implementation
Devices
Connections
Timing
Read
Write

9. Fully-Buffered System
Advantages and Disadvantages
Signal Buffering
Address bus
Data bus
Transceivers
Control signals
Control bus
Contention issues
Terminology
Local bus
Buffered bus
Partial buffering

10. Logic Family Compatibility
Logic family characteristics
Definitions
Logic families
DC noise margins
Driver characteristics
Receiver characteristics
Compatibility
Voltage
Current
Exercises
Capacitive loading
TTL to CMOS

11. Wrapping Up
Reading for next week
Textbook chapters , 11

12. 80C188EB Clock Generator

13. MAX807

14. Basic Read Cycle

15. Basic Write Cycle

16. Bus Cycle State Diagram

17. Bus Cycle Types

18. Read Cycle

19. Write Cycle

20. States & Phases

21. 001A BA mov dx, 1000h

22. 001D C mov [bx], 1234h

23. A mov al, [bx]

24. 0023 EE out dx, al

25. 0024 ED in ax, dx

26. Logic Compatibility Exercises
For the following logic families, determine compatibility, noise margins, and fan-out.
74ALS driving 74AC
74AC driving 74ALS
VOHmin
VIHmin
VOLmax
VILmax
IOHmax
IIHmax
IOLmax
IILmax
74ALS
2.7V
2.0V
0.5V
0.8V
-400uA
+20uA
+8.0mA
-200uA
74AC
4.9V
3.76V
0.7*VCC
0.1V
0.7V
0.3*VCC
-50uA
-24mA
+1uA
+50uA
+24mA
-1uA
Note: For 74AC, top line is with CMOS load, bottom line is with TTL load.

27. TinyLogicTM and Little Logic