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EEE /INSTR/CS F241 ES C263 Microprocessor Programming and Interfacing
Pawan Sharma Lecture
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Today’s Lecture 8086 – Pin out & Bus Operations
Demultiplexing of CPU buses Timing diagrams
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8086 GND 1 40 VCC AD14 2 39 AD15 AD13 3 38 A16/S3 AD12 4 37 A17/S4
S4 S3 characteristics ES SS CS DS S5: status of EI flag bit S6: 0 AD13 3 38 A16/S3 AD12 4 37 A17/S4 AD11 5 36 A18/S5 AD10 6 37 A18/S6 AD9 7 35 BHE/S7 S7: spare status bit AD8 8 33 MN/MX AD7 9 32 RD AD6 10 8086 31 ALE INTA DEN DT/R M/IO WR HLDA HOLD RQ/GT0 AD5 11 30 RQ/GT1 AD4 12 29 LOCK AD3 13 28 S2 AD2 14 27 S1 AD1 15 26 S0 AD0 16 25 QS0 NMI 17 24 QS1 INTR 18 23 TEST CLK 19 22 READY GND 20 21 RESET next
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Minimum & Maximum Modes of Operations
8088/8086 can be configured to work in any of the two modes Minimum Mode MN/MX’ –logic 1 Single processor in system Smaller systems/ Cheaper Maximum Mode MN/MX’ – logic 0 Larger systems – more than one processor e.g. – Numeric Data processor (8087) –co-processor back
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Instruction Cycle Machine Cycle T states MOV BX,[0114H] 8B1E 1401
![Instruction Cycle Machine Cycle T states MOV BX,[0114H] 8B1E 1401](http://slideplayer.com./slide/12643009/76/images/5/Instruction+Cycle+Machine+Cycle+T+states+MOV+BX%2C%5B0114H%5D+8B1E+1401.jpg "Instruction Cycle Machine Cycle T states MOV BX,[0114H] 8B1E 1401")
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One cycle of this clock is called a state
CLK is crystal controlled clock signal sent to 8086 from an external clock generator device such as 8284 One cycle of this clock is called a state A state is measured as rising/falling edge of one clock pulse to rising/falling edge of next clock pulse Different versions of 8086 have maximum clock frequencies of between 5MHz and 10MHz The minimum time of one state will be between 200nS to 100nS A basic operation such as reading a byte from memory /port or writing a byte to a memory/port is called a machine cycle back
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ADDRESS & DATA being MULTIPLEXED on the ADDRESS BUS A0 – A15 + D0 – D15 AD0 – AD15 De-multiplexed externally using latch
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LS273 OE G ALE back
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M/IO’ IOR’ RD’ M/IO’ RD’ WR’ Bus cycle 1 MEMR’ MEMW’ IOR’ IOW’ M/IO’ IOW’ WR’ M/IO’ MEMR’ RD’ M/IO’ MEMW’ WR’ back
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Read Machine Cycle 8086 asserts M/IO’ high if read is from memory and low if read is from port. Send out ALE to latch the address 8086 asserts DT/R’ signal low to put data buffers in receive mode ( why are buffers needed?) Then 8086 sends out the address on AD0 to AD19 and the signal BHE’. Pulls ALE low and address is held on output of latches. Asserts RD’ low to read data from memory or port. RD’ then goes high indicating valid data available on data bus. Asserts DEN’ low to enable the data bus buffers Data put on the data bus by an addressed port or memory will then be able to come in through the buffers to 8086 on the AD0 to AD15 bus
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Buffered Systems Buffering of control/data/addr busses to make signals sufficiently strong to drive various IC chips Pulse leaves IC chip - drop in strength due to parasitic capacitances. As the signal value changes from 0 to 1 or 1 to 0, these unwanted capacitors are charged and discharged. Based on distance between the IC generating the signal & the IC receiving the signal and their input capacitances . More Pins a signal is connected (Fan-out) to, stronger must be the signal Bus buffering Boosting the signals traveling on the bus Unidirectional Buffer - 74LS244 Bidirectional Buffer LS245
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E DIR A Bus Inputs/Outputs B Bus DEN DT/R
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Bus Cycle & Time States Bus cycle defines the basic operation that a µp performs to communicate with ext devices Bus Cycles – MEMR’, MEMW’, IOR’, IOW’ Corresponds to the sequence of events that starts with an address being o/p on the system bus followed by a read/write data transfer During these operations - a series of control signals are also produced by the µp to control the direction and timing of the bus Each bus cycle is made of at least 4 clock periods – called T-states
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Signals of 8086 used during a bus transfer
AD15 – AD0 – Multiplexed Address & Data A19/S6 – A16/S3 – Higher order Address / Status M/IO’ – Indicates whether access is to memory or I/O RD’ - Read Operation from Memory/IO WR’ - Write Operation to Memory/IO ALE - When set – Multiplexed AD0 – AD has address DT/R’ is transmitting/receiving data DEN’ - Enable data buffers connected to 8086
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Bus Timings for a Read Operation
Tw T1 T2 T3 T4 CLK A19-A16/S6–S3 S7 – S3 BHE’/A19 – A16 AD19- AD16 A15-A0 Bus reserved for Data in Data Data Setup Address Setup M/IO’ ALE DT/R’ RD’ DEN’ Memory access time 200 ns 800 ns Bus Timings for a Read Operation
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During write cycle 8086 asserts DT/R’ signal high to put the buffers in the transmit mode
When 8086 asserts DEN’ low to enable the buffers- data o/p from 8086 will pass through the buffers to the addressed port or memory location back
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T1 T2 T3 T4 CLK A19-A16/S6–S3 A19 – A16 S7 – S3 AD19- AD16 A15-A0 Data Address Setup M/IO’ ALE DT/R’ WR’ DEN’ 200 ns 800 ns Bus Timings for a Write Operation
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READY Signal & WAIT States
The READY input causes wait states for slower memory or I/O components. A wait state (Tw) is an extra clocking period, inserted between T2 and T3 to lengthen the bus cycle. If one wait state is inserted, then the memory access time, normally 460ns with a 5MHz clock, is lengthened by one clock period(200 ns) to 660ns.
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A16-A19 S6-S3 BHE’/S7 ALE AD8-AD15 AD0-AD7 MN/MX’ A16-A19 LS373 BHE’ G
OE’ ALE 8086 LS373 AD8-AD15 A8-A15 G OE’ LS373 AD0-AD7 A0-A7 G OE’ MN/MX’ 5V
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RD WR M/IO AD8-AD15 DT/R’ DEN’ AD0-AD7 MN/MX’ MEMR LS244 LOGIC CIRCUIT
MEMW WR IOR M/IO OE’ IOW 8086 LS245 AD8-AD15 D8-D15 DT/R’ DIR OE’ DEN’ LS245 AD0-AD7 D0-D7 DIR OE’ MN/MX’ 5V
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A Fully buffered 8086 system
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