1. Tunnel FETs
Peng Wu
Mar 30, 2017

2. Outline
Introduction
Challenges
Experimental results
Conclusion

3. Outline
Introduction
Challenges
Experimental results
Conclusion

4. Introduction
With continuous scaling down, energy consumption has become a headache for IC industry
VDD scaling limited by leakage current
Pdynamic=CVDD2f
Pleakage=VDDIOFF
MOSFETs: fundamental limitation 300K
due to switching mechanism: thermionic emission over a barrier
VDD
IOFF
(exponetial)
Requires a different switching mechanism
Ionescu, A. M. et al., Nature, 479,

5. Introduction Band-to-band tunneling (BTBT)
Thermal tail in Fermi distribution cut off by energy filter: carriers effectively cooled down
Dmitri Nikonov, in Beyond CMOS

6. Outline
Introduction
Challenges
Experimental results
Conclusion

7. Challenges Projections vs. Realities
Low ION (cannot turn on effectively)
Bad slope / high IOFF (cannot turn off effectively)

8. Challenges ON-current:
Limited by transmission through tunneling barrier
Ionescu, A. M. et al., Nature, 479,
(Direct bandgap)
use optimized structure (e.g. GAA nanowire) and high-K dielectric for tight gate control; use heterojunction
λ: tunneling distance →
m*, Eg: material properties →
use material with small Eg and m*, e.g. III-V
Si: not suitable for TFETs (large Eg and m*, indirect bandgap requires phonon-assisted tunneling → low transmission)

9. Challenges OFF-current Trap-assisted tunneling (TAT)
Traps: impurities, dangling bonds, surface roughness, etc
Need to reduce Dit
Redwan N. Sajjad et al., IEEE TED 63 (11),

10. Challenges OFF-current Trap-assisted tunneling (TAT) Band-tail effect
Heavy doping in source
M. Abul Khayer et al., J. Appl. Phys. 110, (2011)

11. Challenges OFF-current Trap-assisted tunneling (TAT) Band-tail effect
Direct S-D tunneling
For scaled device
P. Wu et al., Proc. of SISPAD, (2015),

12. Challenges OFF-current Trap-assisted tunneling (TAT) Band-tail effect
Direct S-D tunneling
Gate control
GAA nanowire TFET
Better electrostatic control for smaller diameter

13. Outline
Introduction
Challenges
Experimental results
Conclusion

14. Experimental results First sub-60mV/dec TFET: PRL 2004
Channel: carbon nanotube
300K

15. Experimental results: Si TFET
Si TFET (UC Berkeley)
VLSI 2010
Source: NiSi/n+ Si
Channel: i-Si (40nm SOI)
Drain: p-Si
Minimum SS: 46mV/dec
Problem: low ON-current
Kanghoon Jeon et al., VLSI 2010

16. Experimental results: III-V TFET
IEDM 2013
Source: p+ GaAs0.18Sb0.82
Channel: i In0.9Ga0.1As
Drain: n+ In0.9Ga0.1As
Large ION: VDS=0.5V
Problem: bad SS (>200mV/dec)

17. Experimental results: III-V TFET
IEDM 2016
(Best TFET result so far)
20nm
Source: p++ GaAsSb
Channel: n- InAs
Drain: n++ InAs
ION: 10uA/um
SS: 48mV/dec

18. Experimental results: III-V TFET
IEDM 2016
(Best TFET result so far)
Stoichiometry not clear for GaAsSb
Growth condition:
Bulk GaSb/InAs forms broken-gap
Nanowire from broken-gap to staggered-gap
20nm
Source: p++ GaAsSb
Channel: n- InAs
Drain: n++ InAs
Herbert Kroemer, Physica E 20 (2004) 196–203
Lind, E. et al., IEEE JEDS 3 (2014)

19. Experimental results: III-V TFET
IEEE EDL 2016
(Same Lund University group)

20. Experimental results: 2D TFET
Nature 2015
Source: p-Ge
Channel: Bi-layer MoS2
(Drain: MoS2 n-Schottky contact)
Minimum SS: 3.9mV/dec
Average SS: 31.1mV/dec (4 decades)
Scale bar: 5um
Problem: scaling?
~20umx10um
What about 100nmx1um?

21. Experimental results: summary
Si TFET:
Advantages: most developed process → good gate control, low Dit, compatible with current foundry process
Disadvantages: bad intrinsic material properties (large m*, Eg, indirect bandgap) → low ION
III-V TFET:
Advantages: low Eg, low m*, easy to form heterojunction
Disadvantages: control of trap-assisted tunneling and band-tail effect
2D material:
Advantages: ultra-thin body, no body-thickness fluctuation, no dangling bonds
Disadvantages: process needs to be developed (material growth, high-K dielectric, doping method)

22. Conclusion
Tunnel FET: a "drop-in" replacement of MOSFET for low-power applications
Similar switch operation → require less effort in circuit design
Ion lower than MOSFET → not suitable for high-performance applications
Still challenges to be solved
Slope not as steep as predicted
Ion lower than required