1. CSE 5345 – Fundamentals of Wireless Networks

2. Today
Spread Spectrum
Coding and Error Control

3. Spread Spectrum - Transmitter
Input is fed into a channel encoder
Produces analog signal with narrow bandwidth
Signal is further modulated using sequence of digits
Spreading code or spreading sequence
Pseudonoise, or pseudo-random number
Resulting in increased bandwidth of signal

4. Spread Spectrum - Receiver
On receiving end, digit sequence is used to demodulate the spread spectrum signal
Signal is fed into a channel decoder to recover data

5. Spread Spectrum

6. Spread Spectrum - Why Resistance to noise and multipath distortion
Data hiding and encryption
Concurrent transmission for several users

7. Frequency Hoping Spread Spectrum (FHSS)
Transmission over seemingly random frequencies
A number of channels allocated for the FH signal
Width of each channel = bandwidth of input signal
Signal hops from frequency to frequency
At fixed intervals
Transmitter operates in one channel at a time
Bits are transmitted using some encoding scheme
At each successive interval, a new carrier frequency is selected

8. Frequency Hoping Spread Spectrum
Channel sequence dictated by spreading code
Receiver hops in synchronization with transmitter
Advantages
Eavesdroppers hear only unintelligible blips
Attempts to jam signal on one frequency succeed only at knocking out a few bits

9. Frequency Hoping Spread Spectrum

10. FHSS Performance Considerations
Large number of frequencies used
Resistant to interference and jamming
Jammer must jam all frequencies
With fixed power, this reduces the jamming power in any one frequency band

11. Direct Sequence Spread Spectrum (DSSS)
Each bit in original signal is represented by multiple bits in the transmitted signal
Spreading code spreads signal across a wider frequency band
Spread is in direct proportion to number of bits used
One technique combines digital information stream with the spreading code bit stream using exclusive-OR (Figure 7.6)

12. Direct Sequence Spread Spectrum (DSSS)

13. DSSS Using BPSK Multiply BPSK signal,
sd(t) = A d(t) cos(2 fct)
by c(t) [takes values +1, -1] to get
s(t) = A d(t)c(t) cos(2 fct)
A = amplitude of signal
fc = carrier frequency
d(t) = discrete function [+1, -1]
At receiver, incoming signal multiplied by c(t)
Since, c(t) x c(t) = 1, incoming signal is recovered

14. DSSS Using BPSK

15. Code-Division Multiple Access (CDMA)
Basic Principles of CDMA
D = rate of data signal
Break each bit into k chips
Chips are a user-specific fixed pattern
Chip data rate of new channel = kD

16. CDMA Example If k=6 and code is a sequence of 1s and -1s
For a ‘1’ bit, A sends code as chip pattern
<c1, c2, c3, c4, c5, c6>
For a ‘0’ bit, A sends complement of code
<-c1, -c2, -c3, -c4, -c5, -c6>
Receiver knows sender’s code and performs electronic decode function
<d1, d2, d3, d4, d5, d6> = received chip pattern
<c1, c2, c3, c4, c5, c6> = sender’s code

17. 6: Wireless and Mobile Networks
CDMA Encode/Decode
channel output Zi,m
d1 = -1 1 -
Zi,m= di.cm
Data bits
d0 = 1 1 - 1 - 1 -
sender
slot 1
channel
output
slot 0
channel
output
code
slot 1
slot 0
Di = S Zi,m.cm
m=1 M
Received input 1 - 1 -
d0 = 1
d1 = -1
slot 1
channel
output
slot 0
channel
output
code
receiver
slot 1
slot 0
6: Wireless and Mobile Networks

18. [ ]
[ ]
User 1:
User 2:
Channel:
Receiver 1: [ ]*Channel=4=>1
Receiver2: [ ]*Channel=-4=>-1
A*[A1*b+A2*c+A3*d]

19. Coding and Error Control

20. Coping with Data Transmission Errors
Error detection codes
Detects the presence of an error
Automatic repeat request (ARQ) protocols
Block of data with error is discarded
Transmitter retransmits that block of data
Error correction codes, or forward correction codes (FEC)
Designed to detect and correct errors

21. Error Detection Process
Transmitter
For a given frame, an error-detecting code (check bits) is calculated from data bits
Check bits are appended to data bits
Receiver
Separates incoming frame into data bits and check bits
Calculates check bits from received data bits
Compares calculated check bits against received check bits
Detected error occurs if mismatch

22. Error Detection Process

23. Parity Check Parity bit appended to a block of data Even parity
Added bit ensures an even number of 1s
Odd parity
Added bit ensures an odd number of 1s
Example, 7-bit character [ ]
Even parity [ ]
Odd parity [ ]

24. Cyclic Redundancy Check (CRC)
Transmitter
For a k-bit block, transmitter generates an (n-k)-bit frame check sequence (FCS)
Resulting frame of n bits is exactly divisible by predetermined number
Receiver
Divides incoming frame by predetermined number
If no remainder, assumes no error
Skip

25. CRC using Modulo 2 Arithmetic
Exclusive-OR (XOR) operation
Parameters:
T = n-bit frame to be transmitted
D = k-bit block of data; the first k bits of T
F = (n – k)-bit FCS; the last (n – k) bits of T
P = pattern of n–k+1 bits; this is the predetermined divisor
Q = Quotient
R = Remainder

26. CRC using Modulo 2 Arithmetic
For T/P to have no remainder, start with
Divide 2n-kD by P gives quotient and remainder
Use remainder as FCS

27. CRC using Modulo 2 Arithmetic
Does R cause T/P have no remainder?
Substituting,
No remainder, so T is exactly divisible by P

28. CRC using Polynomials All values expressed as polynomials
Dummy variable X with binary coefficients

29. CRC using Polynomials Widely used versions of P(X) CRC–12 CRC–16
X12 + X11 + X3 + X2 + X + 1
CRC–16
X16 + X15 + X2 + 1
CRC – CCITT
X16 + X12 + X5 + 1
CRC – 32
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

30. CRC using Digital Logic
Dividing circuit consisting of:
XOR gates
Up to n – k XOR gates
Presence of a gate corresponds to the presence of a term in the divisor polynomial P(X)
A shift register
String of 1-bit storage devices
Register contains n – k bits, equal to the length of the FCS

31. Digital Logic CRC

32. Wireless Transmission Errors
Error detection requires retransmission
Detection inadequate for wireless networks
Error rate on wireless link can be high
=> a large number of retransmissions
Long propagation delay
Long transmission time (slow data rate)
Wireless Channel is error prone
Error Correction instead of only error detection  Coding

33. Block Error Correction Codes
Transmitter
Forward error correction (FEC) encoder maps each k-bit block into an n-bit block codeword
Codeword is transmitted; analog for wireless transmission
Receiver
Incoming signal is demodulated
Block passed through an FEC decoder

34. Forward Error Correction Process

35. FEC Decoder Outcomes No errors present
Codeword produced by decoder matches original codeword
Decoder detects and corrects bit errors
Decoder detects but cannot correct bit errors; reports uncorrectable error
Decoder detects no bit errors, though errors are present

36. Block Code Principles Hamming distance:
for 2 n-bit binary sequences, the number of different bits
E.g., v1=011011; v2=110001; d(v1, v2)=3
Redundancy – ratio of redundant bits to data bits
Code rate – ratio of data bits to total bits (k/n)

37. Block Code Principles Coding gain
the reduction in the required Eb/N0 to achieve a specified BER of an error-correcting coded system

38. Hamming Code Designed to correct single bit errors
Family of (n, k) block error-correcting codes with parameters:
Block length: n = 2m – 1
Number of data bits: k = 2m – m – 1
Number of check bits: n – k = m
Minimum distance: dmin = 3
Single-error-correcting (SEC) code
SEC double-error-detecting (SEC-DED) code
Inserted at 2i position

39. Hamming Code Process Encoding: k data bits + (n -k) check bits
Decoding: compares received (n -k) bits with calculated (n -k) bits using XOR
Resulting (n -k) bits called syndrome word
Syndrome range is between 0 and 2(n-k)-1
Each bit of syndrome indicates a match (0) or conflict (1) in that bit position

40. Hamming Code Process - Example
Data:

41. Hamming Code Process - Example
Bit 6 error