1. Principles & Applications
Digital Electronics
Principles & Applications
Seventh Edition
Roger L. Tokheim
Chapter 9
Shift Registers
©2008 The McGraw-Hill Companies, Inc. All rights reserved.

2. INTRODUCTION Overview of Shift Registers
Characteristics of Shift Registers
Serial/Parallel Data Conversion
Serial Load Shift Register
Parallel Load Shift Register
Recirculating Shift Register
Using the Shift Register IC
Digital Roulette Game
Troubleshooting Hints

3. Overview of Shift Registers
A shift register is a sequential logic device made up of flip-flops that allows parallel or serial loading and serial or parallel outputs as well as shifting bit by bit.
Common tasks of shift registers:
Serial/parallel data conversion
UART (an example)
Time delay
Ring counter
Twisted-ring counter or Johnson counter
Memory device

4. Characteristics of Shift Registers
Number of bits (4-bit, 8-bit, etc.)
Loading
Serial
Parallel (asynchronous or synchronous)
Common modes of operation.
Parallel load
Shift right-serial load
Shift left-serial load
Hold
Clear
Recirculating or non-recirculating

5. Serial/Parallel Data Conversion
Shift registers can be used to convert from serial-to-parallel or the reverse from parallel-to-serial.
Parallel in
Parallel out
Serial in
Parallel out
Serial out
Parallel in
Serial in
Serial out

6. QUIZ Q#1- This represents a ___ register. a. Parallel-in, parallel-out
b. Serial-in, parallel-out
Q#2- This represents a ___ register.
a. Parallel-in, parallel-out
b. Serial-in, serial-out
Q#3- This represents a ___ register.
a. Parallel-in, serial out
b. Serial-in, parallel-out
Q#4- This represents a ___ register.
a. Parallel-in, serial out
b. Parallel-in, parallel-out
ANS: serial-in parallel-out
ANS: serial-in serial-out
ANS: parallel-in serial-out
ANS: parallel-in parallel-out

7. Serial Load Shift Register
Parallel outputs here.
Order= A B C D
Clock Pulse 6
Clear = 1
Data = 0
Clock Pulse 7
Clear = 1
Data = 1
Clock Pulse 8
Clear = 1
Data = 0
Clock Pulse 2
Clear = 1
Data = 1
Clock Pulse 5
Clear = 1
Data = 0
Clock Pulse 1
Clear = 0
Data = 1
Clock Pulse 4
Clear = 1
Data = 0
Clock Pulse 3
Clear = 1
Data = 1
Inputs here:
(1) Data
(2) Clock
(3) Clear
4-bit
serial-in
parallel out
shift right
shift register
Clock input:
Positive-edge
triggering
Clear input:
Active = 0
Deactivated = 1
Note the use of D FFs.
Clock (CLK) inputs wired in parallel.
Clear (CLR) inputs can be activated with LOW
or disabled with HIGH.
Preset (PS) inputs deactivated.

8. QUIZ A: Serial-in, parallel-out A: 1001 A: 0010 A: 0100 A: 1100
QUESTION #5
What is the 4-bit output (bit A on left, D on right) after pulse 4?
QUESTION #2
What is the 4-bit output (bit A on left, D on right) after pulse 1?
QUESTION #1
This is a ___ type shift register.
A. Serial-in, parallel out
B. Parallel-in, serial-out
QUESTION #7
What is the 4-bit output (bit A on left, D on right) after pulse 6?
QUESTION #4
What is the 4-bit output (bit A on left, D on right) after pulse 3?
QUESTION #6
What is the 4-bit output (bit A on left, D on right) after pulse 5?
QUESTION #3
What is the 4-bit output (bit A on left, D on right) after pulse 2?
A: Serial-in, parallel-out
A: 1001
A: 0010
A: 0100
A: 1100
A: 1000
A: 0000
Clock Pulse 6
Clear = 1
Data = 1
Clock Pulse 4
Clear = 1
Data = 0
Clock Pulse 5
Clear = 1
Data = 1
Clock Pulse 1
Clear = 0
Data = 1
Clock Pulse 2
Clear = 1
Data = 1
Clock Pulse 3
Clear = 1
Data = 0

9. Parallel Load Shift Register
Outputs here.
Order= A B C D
Parallel data
inputs
(Active LOW)
Recirculating
lines:
Pass data from
FFD to FFA
on each
clock pulse.
Clock input- H-to-L
Note the
recirculating
lines.
Clear input- Active LOW
Note the use of J-K FFs.
Clock (CLK) inputs wired in parallel.
Clear (CLR) input activated with LOW.
Parallel load inputs (A,B,C,D) are active LOW.

10. Recirculating Shift Register
Clock pulse 8
Clear input= 1
Parallel data inputs=
only B active
Clock pulse 7
Clear input= 0
Parallel data inputs=
all inactive
Clock pulse 1
Clear input= 0
Parallel data inputs=
only D activated
Clock pulse 6
Clear input= 1
Parallel data inputs=
all inactive
Clock pulse 3
Clear input= 1
Parallel data inputs=
all inactive
Clock pulse 5
Clear input= 1
Parallel data inputs=
all inactive
Clock pulse 2
Clear input= 1
Parallel data inputs=
C & D activated
Clock pulse 4
Clear input= 1
Parallel data inputs=
all inactive

11. QUIZ
Q#1- After clock pulse 1, the output from the shift register
will be ___.
Q#2- After clock pulse 2, the output from the shift register
will be ___.
Q#3- After clock pulse 3, the output from the shift register
will be ___.
Q#4- After clock pulse 4, the output from the shift register
will be ___.
Q#5- After clock pulse 5, the output from the shift register
will be ___.
Q#6- After clock pulse 6, the output from the shift register
will be ___.
Clock pulse 6
Clear input= 1
Parallel data inputs=
none active
Clock pulse 1
Clear input= 0
Parallel data inputs=
none active
Clock pulse 5
Clear input= 1
Parallel data inputs=
none active
Clock pulse 3
Clear input= 1
Parallel data inputs=
none active
Clock pulse 4
Clear input= 1
Parallel data inputs=
none active
Clock pulse 2
Clear input= 1
Parallel data inputs=
B and C active

12. Universal Shift Register IC
Outputs here
Clear input
active LOW
Serial data Right input
used during
Serial Load Right
mode of operation
Parallel data inputs
Order: A, B, C, D
during Parallel loading
Serial data Left input
used during
Serial Load Left
mode of operation
Clock input
L-to-H triggering
Mode Controls:
Hold
Parallel load
Shift right
Shift left
74194 Universal 4-bit Shift Register IC.
Modes of operation: Hold, Parallel load, Shift right & Shift left.
An active LOW Clear (CLR) input overrides all others.

13. Using the 74194 Shift Register IC
CLR = 1
Serial R = X
Parallel Load=
Serial L = X
Clock pulse 6
(L-to-H)
S0= 1
S1= 1
CLR = 1
Serial R = X
Parallel Load=
Serial L = 1
Clock pulse 7
(L-to-H)
S0= 0
S1= 1
CLR = 1
Serial R = X
Parallel Load=
Serial L = 0
Clock pulse 8
(L-to-H)
S0= 0
S1= 1
CLR = 1
Serial R = 0
Parallel Load=
Serial L = X
Clock pulse 4
(L-to-H)
S0= 0
S1= 0
CLR = 1
Serial R = X
Parallel Load=
Serial L = X
Clock pulse 1
(L-to-H)
S0= 1
S1= 1
CLR = 0
Serial R = 0
Parallel Load=
Serial L = X
Clock pulse 5
(L-to-H)
S0= 1
S1= 1
CLR = 1
Serial R = 0
Parallel Load=
Serial L = X
Clock pulse 2
(L-to-H)
S0= 1
S1= 0
CLR = 1
Serial R = 0
Parallel Load=
Serial L = X
Clock pulse 3
(L-to-H)
S0= 1
S1= 0
X = Irrelevant

14. QUIZ ? ? ? ? A: Universal A: Clear, 0 0 0 0 A: Parallel load, 0 1 0 0
QUESTION #1
The IC could be described as a 4-bit (shift right, universal)
shift register.
QUESTION #3
What is the mode of operation during and the output of the
shift register after pulse 2?
QUESTION #2
What is the mode of operation during and the output of the
shift register after pulse 1?
QUESTION #4- What is the mode of operation during and the output of the
shift register after pulse 3?
QUESTION #5
What is the mode of operation during and the output of the
shift register after pulse 4?
QUESTION #7
What is the mode of operation during and the output of the
shift register after pulse 6?
QUESTION #6
What is the mode of operation during and the output of the
shift register after pulse 5?
A: Universal
A: Clear,
A: Parallel load,
A: Shift right,
A: Shift left,
A: Hold,
A: Shift left,
? ? ? ?
CLR = 1
Serial R = 0
Parallel Load=
Serial L = X
Clock pulse 2
(L-to-H)
S0= 1
S1= 1
CLR = 1
Serial R = X
Parallel Load=
Serial L = 1
Clock pulse 6
(L-to-H)
S0= 0
S1= 1
CLR = 1
Serial R = 0
Parallel Load=
Serial L = X
Clock pulse 4
(L-to-H)
S0= 0
S1= 0
CLR = 1
Serial R = X
Parallel Load=
Serial L = 1
Clock pulse 5
(L-to-H)
S0= 0
S1= 1
CLR = 0
Serial R = X
Parallel Load=
Serial L = X
Clock pulse 1
(L-to-H)
S0= 1
S1= 1
CLR = 1
Serial R = 0
Parallel Load=
Serial L = X
Clock pulse 3
(L-to-H)
S0= 1
S1= 0

15. Digital Roulette Game 1 1 1 1 1 Spin Wheel 1 input 1 1 +5V Audio
Amplifier 1 1 1 1 1 1 1 1
Power-up
Initializing
Circuit
Spin
Wheel
input
+5V
Voltage
Controlled
Oscillator
(VCO)
8-bit
Ring Counter
(shift register)
Simulated
Roulette
Display

16. ANS: voltage-controlled oscillator (VCO)
QUIZ
Q#1- The block at A in the digital roulette game
contains a(n) ___ circuit.
Q#2- The block at B in the digital roulette game
contains a(n) ___ circuit.
Q#3- The block at C in the digital roulette game
contains a(n) ___ circuit which is a type of 8-bit shift register.
ANS: voltage-controlled oscillator (VCO)
ANS: audio amplifier
ANS: ring counter B C A

17. Simple Troubleshooting Hints
Feel top of IC to determine if it is hot
Look for broken connections, signs of excessive heat
Smell for overheating
Check power source
Trace path of logic through circuit
Know the normal operation of the circuit

18. QUIZ
The most important factor in successful troubleshooting is a good knowledge of the circuit’s normal operation. (True or False)
True
2. The first three steps in troubleshooting are to use your senses to (1) __________ the top of the ICs for overheating, (2) look for broken connections, and (3) smell for signs of overheating.
feel
3. The fourth step in troubleshooting is to use a(n) __________ (logic probe, tachometer) to check the power sources to the IC.
logic probe
4. The fifth step in troubleshooting is to trace the path of logic through the circuit. (True or False)
True

19. REVIEW Overview of Shift Registers Characteristics of Shift Registers
Serial/Parallel Data Conversion
Serial Load Shift Register
Parallel Load Shift Register
Recirculating Shift Register
Using the Shift Register IC
Digital Roulette Game
Troubleshooting Hints