1. Computer Sciences Department University of Wisconsin-Madison
Architectural Characterization of an IBM RS6000 S80 Server Running TPC-W Workloads
Lei Yang & Shiliang Hu
Computer Sciences Department University of Wisconsin-Madison

2. Outline
TPC-W Benchmarks in Java
IBM RS6000 S80 Enterprise Server
Hardware Counters in S80
Experiment Results
Problems and Future work
Conclusions

3. TPC-W benchmark
TPC-W is the TPC’s new benchmark for Transactional Web Environments (E-Commerce) Modeling an online book store similar to
Browsing
Shopping
Ordering
Transactional Web Environment:
Web serving of static and dynamic content
Online Transaction processing (OLTP)
Some decision support (DSS)

4. System Configuration:

5. IBM RS6000 S80 Enterprise Server
6 RS64-III Pulsar processors (451MHz)
4-issure in-order SuperScalar, 128KB L1 I-Cache, 128KB L1 D-Cache, 8MB L2 Cache.
No Branch Prediction, Aggressive early branch resolution
2 coarse grain Multithreading.
8GB main memory

6. Hardware Counters in S80 Kernel extension to AIX 4.3
Hardware Counter API

7. Results: IPC for RBE, Java Web Server and DB2

8. Results: CPU Cycle Counts
The DB2 cycles component for the ordering mix is significantly larger than that of the other two mixes.
RBE cycles are dominant in browsing and shopping mixes.

9. Results: Instruction Dispatch
Browsing Mix
Dispatch Percentage %
Dispatch Percentage %

10. Results: Instruction Dispatch
Shopping Mix
Dispatch Percentage %

11. Results: Instruction Dispatch
Ordering Mix
Dispatch Percentage %

12. Results: Instruction Mix
Browsinging Mix
Instruction type Percentage %

13. Results: Instruction Mix
Shopping Mix
Instruction type Percentage %

14. Results: Instruction Mix
Ordering Mix
Instruction type Percentage %

15. Results: Branch Behavior
Browsing Mix
Shopping Mix
Branches conditional taken
Branch to link register taken
Branch to counter taken
Absolute branches
Branches unconditional
Branches conditional not taken
Zero cycle branch not taken
Zero cycle branch taken

16. Results: Branch Behavior
Ordering Mix
Branches conditional taken
Branch to link register taken
Branch to counter taken
Absolute branches
Branches unconditional
Branches conditional not taken
Zero cycle branch not taken
Zero cycle branch taken

17. Results: Cache Behavior
Browsing Mix
Shopping Mix
Latency/cycles
L1 I cache miss duration latency
L1 D cache miss duration latency

18. Results: Cache Behavior
Shopping Mix
Ordering Mix
Latency/cycles
L1 I cache miss duration latency
L1 D cache miss duration latency

19. Results: Cache Behavior

20. Results: Cache Behavior
Browsing Mix
Shopping Mix
Ordering Mix
Count
L2 miss count per instruction
L1 I cache miss count per instruction
L1 D cache miss count per instruction

21. Problems & Future Works

22. Conclusions

23. Acknowledgement