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Lecture 10: TI MSP430 Timers and Capture Modes
ECE 447 Fall 2009 Lecture 10: TI MSP430 Timers and Capture Modes
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Timer_A Overview Timer Block Capture/compare channels
The core, based on 16-bit register TAR Can chose sources for clock and freq division Timer block has no output Flag TAIFG is raised when counter returns to 0 Capture/compare channels Capture an input, record value in TAR triggered by TACCRn Compare TAR with the value stored in TACCRn Request an Interrupt by setting its flag TACCRn CCFIG Sample an input at a compare event
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ECE 447: MSP430 Timer_A System
Generating delays - imposing a specific delay between two points in the program by polling. label 1 instr1 instr2 delay label2 instrN
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ECE 447: MSP430 Timer_A System
2. Input capture - measuring the time between signal edges start stop start stop 3. Output compare - generating signals with the given timing characteristics single pulse periodical signal pulse width period
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ECE 447: MSP430 Timer_A System
4. Real Time Clock– Produce a periodic signal for the MSP430. period The Real Time Clock Interrupt implements a hardware based time of day clock that can be used by the software.
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ECE447: MSP430 Timer I/O Pins and Channels - 4618
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ECE447: MSP430 Compare/Capture Block Diagram.
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MSP430xx4xx Implementation of Timer_A
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Timer_A Interrupt Schematic
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Timer_A MSP430xx4xx Registers
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TACTL: Timer_A Control Register
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TAR: Timer_A Register
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TACCRx: Timer_A Capture/Compare Register
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TACCTLx: Capture/Compare Control Register
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TAIV: Timer_A Interrupt Vector Register
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ECE447: MPS430 Timer_A input clocks and dividers
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ECE447: Measuring Pulse Widths
100 s < width < Configured Period (previous table) start stop width 100 s start stop width Configured Period (previous table) start stop Timer overflows
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ECE 447: Measuring intervals <216 clock cycles
FFFF stop start
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ECE 447: Measuring intervals <216 clock cycles (overflow)
FFFF start stop
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ECE 447: Measuring intervals >216 clock cycles
FFFF stop R start
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ECE 447: Measuring intervals >216 clock cycles
3 N=4 FFFF R1 start R1+R2=R stop R2
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