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Paulo Moreira TWEPP 24th September 2009

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1 Paulo Moreira TWEPP 24th September 2009 http://cern.ch/proj-gbt
The GBT Project Paulo Moreira TWEPP 24th September 2009

2 GBT – People Luiz Amaral – CERN, Switzerland Sophie Baron – CERN, Switzerland Sandro Bonacini – CERN, Switzerland Jean-Pierre Cachemiche – CPPM, France Bruno Checcucci – INFN, Italy Jorgen Christiansen – CERN, Switzerland Ozgur Cobanoglu – CERN, Switzerland Federico Faccio – CERN, Switzerland Philippe Farthouat – CERN, Switzerland Tim Fedorov – SMU, USA Rui Francisco – CERN, Switzerland Alessandro Gabrielli – INFN, Italy Tullio Grassi – University of Maryland Ping Gui – SMU, USA Paul Hartin – SMU, USA Kostas Kloukinas – CERN, Switzerland Gianni Mazza – INFN, Italy Mohsine Menouni – CPPM, France Alessandro Marchioro – CERN, Switzerland Frederic Marin – CPPM, France Stefano Meroli – INFN, Italy Paulo Moreira – CERN, Switzerland Christian Paillard – CERN, Switzerland Nataly Pico – SMU, USA Antonio Ranieri – INFN, Italy Giuseppe De Robertis – INFN, Italy Angelo Rivetti – INFN, Italy Sergio Silva – CERN, Switzerland Csaba Soos – CERN, Switzerland Filipe Sousa – CERN, Switzerland Jan Troska – CERN, Switzerland Francois Vasey – CERN, Switzerland Ken Wyllie – CERN, Switzerland Bryan Yu – SMU, USA

3 Outline GBT at TWEPP 2009 Radiation Hard Optical Link Architecture
GBTX-TO-FRONTEND: Parallel Modes E-Link Modes The GBT Chipset: Gigabit Laser Driver (GBLD) Gigabit Trans-Impedance Amplifier (GBTIA) Gigabit – Serializer/De-serializer (GBT-SERDES) E-Links E-Port Scalable Low-Voltage Signalling (SLVS) SLVS Transceiver Macrocell GBT on FPGAs GBT Specifications GBT project schedule

4 The GBT at TWEPP 2009 Thursday, 24 September 2009
B5 - Optoelectronics and Links 11: :25 (GBT) Paulo MOREIRA, “The GBT project” 11: :50 (VL) Jan TROSKA, “The Versatile Transceiver Proof of Concept” A5 – ASICS: 12: :40 (GBT) Giovanni MAZZA, “A 5 Gb/s Radiation Tolerant Laser Driver in 0.13 um CMOS technology” 12: :05 (GBT) Mohsine MENOUNI, “The GBTIA, a 5 Gbit/s radiation-hard optical receiver for the SLHC upgrades” POSTERS SESSION Poster 19 (GBT) Ozgur COBANOGLU, “A Radiation Tolerant 4.8 Gb/s Serializer for the Giga-Bit Transceiver” Poster 28 (GBT) Sandro BONACINI, “e-link: A Radiation-Hard Low-Power Electrical Link for Chip-to-Chip Communication” Poster 64 (GBT) Alessandro GABRIELLI, “The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHC experiments” Poster 115 (VL) Sergio SILVA, Characterization of Semiconductor Lasers for Radiation Hard High Speed Transceivers Friday, 25 September 2009 Session 6 - Programmable Logic, Boards, Crates and Systems 10: :35 (GBT) Frederic MARIN, “Implementing the GBT data transmission protocol in FPGAs” 10: :00 (VL) Csaba SOOS, “FPGA-based Bit-Error-Ratio Tester for SEU-hardened Optical Links”

5 Radiation Hard Optical Link Architecture
Defined in the “DG White Paper” “Work Package 3-1” Objective: Development of an high speed bidirectional radiation hard optical link Deliverable: Tested and qualified radiation hard optical link Duration: 4 years (2008 – 2011) Radiation Hard Optical Link: Versatile link project: Opto-electronics Radiation hardness Functionality testing Packaging GBT project: ASIC design Verification On-Detector Custom Electronics & Packaging Radiation Hard Off-Detector Commercial Off-The-Shelf (COTS) Custom Protocol

6 GBTX-TO-FRONTEND: Parallel Modes
P-Bus Mode: Simple parallel interface 40-bit wide bus Bidirectional Double Data Rate (DDR) B-Bus Mode: A byte-bus mode is also available Up to five independent buses can be used simultaneously Electrical levels: SLVS electrical level: 100 W termination 400 mV differential 200 mV common mode ILOAD = ±2 mA JEDEC standard, JESD8-13 Scalable Low-Voltage Signalling for 400 mV (SLVS-400)

7 GBTX-TO-FRONTEND: E-Link Modes
GBT/Frontend interface: Electrical links (e-link) Serial Bidirectional Up to 40 links Programmable data rate: Independently in five groups Independently for up/down links 80 Mb/s, 160 Mb/s and 320 Mb/s Lanes: To achieve > 320 Mb/s Two or more e-links can be grouped forming a “lane” Slow control channel: 80 Mb/s E-Link: Three pairs: DOUT/DIN/CLK SLVS E-Links will be handled by E-ports: Electrically “Protocol” Package (preliminary): BGA: 361 – PINS 16 mm x 16 mm, 0.8 mm pitch SEU tolerant

8 The GBT Chipset GBTX Frontend Electronics Radiation tolerant chipset:
GBTIA: Transimpedance optical receiver GBLD: Laser driver GBTX: Data and Timing Transceiver GBT-SCA: Slow control ASIC Supports: Bidirectional data transmission Bandwidth: Line rate: 4.8 Gb/s Effective: 3.36 Gb/s The target applications are: Data readout TTC Slow control and monitoring links. Radiation tolerance: Total dose Single Event Upsets GBTIA GBLD GBTX GBT-SCA Frontend Electronics Data<119:0> Clock<7:0> Control<N:0>

9 GBLD Main specs: Packaging: Engineers : Status:
Bit rate 5 Gb/s (min) Modulation: current sink Single-ended/differential Laser modulation current: 2 to 12 mA Laser bias: 2 to 43 mA “Equalization” Pre-emphasis/de-emphasis Independently programmable for rising/falling edges Supply voltage: 2.5 V Die size: 2 mm × 2 mm I2C programming interface Packaging: Part of the versatile link project Engineers : Gianni Mazza – INFN, Italy Angelo Rivetti – INFN, Italy Ken Wyllie – CERN, Switzerland Status: Chip fabricated and tested A re-spin is necessary Giovanni MAZZA et al., “A 5 Gb/s Radiation Tolerant Laser Driver in 0.13 um CMOS technology”

10 GBLD – Test Results The layout issues are being corrected: GBL tests:
Chip is “functional” however the bandwidth falls short of specifications! Fortunately the pre-emphasis circuit is working fine, allowing to partially recover the bandwidth! The problem has now been identified: Parasitic capacitance evaluation Layout symmetry The layout issues are being corrected: Submission: 9th of November 2.5 Gb/s 5 Gb/s

11 GBTIA Main specs: Packaging: Engineers : Status:
Bit rate 5 Gb/s (min) Sensitivity: 20 μA P-P (10-12 BER) Total jitter: < 40 ps P-P Input overload: 1.6 mA (max) Dark current: 0 to 1 mA Supply voltage: 2.5 V Power consumption: 250 mW Die size: 0.75 mm × 1.25 mm Packaging: Part of the versatile link project Engineers : Ping Gui – SMU, USA Mohsine Menouni – CPPM, France Status: Chip fabricated and tested Chip fully meets specifications! Radiation tolerance proven! Work has started to encapsulate the GBTIA + PIN-diode in a TO Package (Versatile link project) Mohsine MENOUNI et al., “The GBTIA, a 5 Gbit/s radiation-hard optical receiver for the SLHC upgrades”

12 GBTIA – Test Results http://cern.ch/proj-gbt Paulo.Moreira@cern.ch
-6 dBm -18 dBm (specs: -17 dBm)

13 GBT-SERDES http://cern.ch/proj-gbt Paulo.Moreira@cern.ch Engineers:
Ozgur Cobanoglu - CERN, Switzerland Federico Faccio - CERN, Switzerland Rui Francisco – CERN, Switzerland Ping Gui – SMU, USA Alessandro Marchioro - CERN, Switzerland Paulo Moreira - CERN, Switzerland Christian Paillard - CERN, Switzerland Ken Wyllie - CERN, Switzerland

14 Forward Error Correction (FEC)
High rates of Single Event Upsets (SEU) are expected for SLHC links: Particle “detection” by Photodiodes used in optical receivers. SEUs on PIN-receivers, Laser-drivers and SERDES circuits Experimental results confirmed that for Error-rates below Error Correction is mandatory (J. Troska et al.) ! Upsets lasting for multiple bit periods have been observed Proposed code: Interleaved Reed-Solomon double error correction 4-bit symbols (RS(15,11)) Interleaving: 2 Error correction capability: 2 Interleaving × 2 RS = 4 symbols  16-bits Code efficiency: 88/120 = 73% Line speed: 4.80 Gb/s Coding/decoding latency: one 25 ns cycle GBT frame efficiency: 70% A line code is always required for DC balance and synchronization For comparison, the Gigabit Ethernet frame efficiency is 80% (at the physical level) At a small penalty (10%, when compared with the Gigabit Ethernet) the GBT protocol will offer the benefits of Error Detection and Correction BER BER

15 GBT-Serializer Serializer: Data path: Clock divider: PLL: Engeneers:
4.8 Gb/s 120-bit shift register 3 × 40-bit shift register (f=1.6 GHz) 3-to-1 fast multiplexer (f=4.8 GHz) Data path: No SEU protection SEUs handled by the Reed-Solomon CODEC Clock divider: Divide by 120 f = 4.8 GHz Triple voted for SEU robustness PLL: SEU hardened VCO Engeneers: Ozgur Cobanoglu - CERN, Switzerland Federico Faccio - CERN, Switzerland Paulo Moreira - CERN, Switzerland Ozgur COBANOGLU et al, “A Radiation Tolerant 4.8 Gb/s Serializer for the Giga-Bit Transceiver”

16 GBT-Serializer Clock divider: TMR in the counter mandatory: VCO:
A “missing” count on the clock divider unlocks the PLL resulting in a burst of errors lasting for “ms” TMR in the counter mandatory: A voter + a static DFF is far to slow! Even a voter + a dynamic DFF will not pass the corner simulations! A new “voted DFF” is proposed and used in the GBT-SERDES VCO: Depending on the charge injected, an SEU can stop the VCO oscillations for a few cycles! SEUs were modeled by current pulses injecting 300 fC in 10 ps The VCO current is set so that an SEU event causes a phase shift which is a fraction of the bit period. Penalty: high power consumption.

17 GBT-CDR Dual PLL CDR Loop: Half-Rate:
1st Loop: Frequency centering PLL 2nd Loop: CDR Allows to reduce the CDR VCO gain for lower Jitter Half-Rate: Phase-detector Frequency-detector Constant latency frame alignment circuit As for the serializer: Unprotected data path TMR clock divider SEU hardened VCO Engineers: Ozgur Cobanoglu - CERN, Switzerland Federico Faccio - CERN, Switzerland Rui Francisco – CERN, Switzerland Paulo Moreira - CERN, Switzerland

18 Phase-Shifter X 1 X 8 (X4 in the GBT-SERDES) Main features:
8 – channels (4 in the GBT-SERDES prototype) 1 PLL + Counter generates the three frequencies: 40 / 80 and 160 MHz 1 DLL per channel Mixed digital/analogue phase shifting technique: Coarse deskewing – Digital Fine deskewing – Analogue Power consumption: 5.6 mW/channel (simulated) Differential non-linearity: <6.7% LSB Integral non-linearity: INL<6.5% LSB Engineers : Ping Gui – SMU, USA Tim Fedorov – SMU, USA Paul Hartin – SMU, USA Nataly Pico – SMU, USA Bryan Yu – SMU, USA

19 Slow Control & Monitoring ASIC: GBT - SCA
GBT-SCA Main specs: Dedicated to slow control functions Interfaces with the GBTX using a dedicated E-link port Communicates with the control room using a protocol carried (transparently) by the GBT Implements multiple protocol busses and functions: I2C, JTAG, Single-wire, parallel-port, etc… Implements environment monitoring functions: Temperature sensing Multi-channel ADC Engineers: Alessandro Gabrielli – INFN, Italy Kostas Kloukinas – CERN, Switzerland Alessandro Marchioro – CERN, Switzerland Antonio Ranieri – INFN, Italy Giuseppe De Robertis – INFN, Italy Filipe Sousa – CERN, Switzerland Status Specification work undergoing: 1st Draft already available RTL design undergoing Tape-out: 2010 Alessandro GABRIELLI et al., “The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHC experiments”

20 E-Links: e-port 20 The FE interfaces with the GBTX through an e-port
The e-port handles: The physical interface; The multiple data rates; The lanes (for bandwidth > 320 Mb/s) Line coding: Clock recovery (if required) AC coupling (if required) The user application does not have to care about the frame formats in full detail: It s done through a standard protocol: Atlantic interface proposed ( atlantic.html) Fixed latency needs to be considered! An E-Link Port Adaptor (EPA) “macro” will be available for integration in the front-end ASICs Engineers: Sandro Bonacini – CERN, Switzerland Kostas Kloukinas – CERN, Switzerland Specification work in progress Two “tentative” protocols “proposed”: 7B/8B Balanced Fixed latency Suitable for Trigger commands links RTL code under development High-Level Data Link Control (HDLC) Packet oriented data Bandwidth efficiency (~96%) Non-fixed latency Suitable for slow control and data links RTL code ready To be specified Clock recovery and phase alignment Lanes support 20

21 SLVS Tests SLVS (Scalable Low Voltage Standard)
JEDEC standard: JESD8-13 Main features: 2 mA Differential max Line impedance: 100 Ohm Signal: mV Common mode ref voltage: 0.2V Tests based on the LM4308 component from National Semiconductor: 18-bit CPU interface chip Complete SERDES, configurable as transmitter or receiver Various types of transmission media tested: Kapton PCB Ethernet cable Test equipment Bidirectional link FPGAs perform pseudo-random data generation and checking Sandro BONACINI et al., “e-link: A Radiation-Hard Low-Power Electrical Link for Chip-to-Chip Communication”

22 PRELIMINARY SLVS Transceiver Receiver Electrical Specifications
Power Supply: 1.2V to 1.5V Power Dissipation: 320Mbs power down Transmitter Power Supply: 1.2V to 1.5 V 320Mbs power down Engineer Sandro Bonacini – CERN, Switzerland Status: Chip submitted MOSIS July MPW Electrical Specifications Electrical Specifications Programmable Output Current

23 GBT on FPGAs Firmware: GBT-SERDES successfully implemented in FPGAs:
Scrambler/ Descrambler + Encoder/ Decoder + Serializer/CDR FPGA Tested: XILINX Virtex-4FX ALTERA StratixII GX Ongoing work: Optimization of use of resources Detailed implementation is device dependent Fixed and “deterministic” latency Firmware: Reference designs will be available on both Xilinx and Altera devices Engineers: Sophie Baron – CERN, Switzerland Jean-Pierre Cachemiche – CPPM, France Frederic Marin– CPPM, France Csaba Soos – CERN, Switzerland Xilinx Gb/s Altera + opto TRx Gb/s Frederic MARIN et al, “Implementing the GBT data transmission protocol in FPGAs” Csaba SOOS, “FPGA-based Bit-Error-Ratio Tester for SEU-hardened Optical Links”

24 GBT Specifications Link specification group: Formed in 2008 Members:
Electronics coordinators of: ALICE, ATLAS, CMS and LHCb Five members of the Radiation Hard Optical Link (RHOL) project “Mandate”: Identify the “GBT” needs of each experiment for the SLHC upgrade Discuss the specification documents (before they are distributed within the collaborations). Meetings: 1st meeting (CERN – 2008/04/17) ALICE, ATLAS, CMS and LHCb electronics coordinators presented outlooks of their requirements for SLHC. 2nd meeting (CERN – 2008/11/14) GBT system proposal was presented to the electronics coordinators. 3rd meeting (CERN – 2009/05/05) Link specification feedback Documents: Share point web site created (2008): Specification documents: GBTX specifications (V1.0, January 2009) GBTIA specifications (V1.7, May 2008) GBLD specifications (V2.0, July 2008) GBT-SCA specifications (V1.5, June 2008) E-Port IP 7B8B specifications (V0.1, December 2008) E-Port IP Core specifications (V0.2, January 2009) E-Port IP HDLC specs (V0.2, January 2009)

25 Project Schedule 2008 Design and prototyping of performance critical building blocks: GBTIA, GBLD, Serializer, De-Serializer, Phase Shifter First tests of optoelectronics components SEU tests on PIN receivers Proceed with the link specification meetings General link specification 2009 Design/prototype/test of basic serializer/de-serializer (GBT-SERDES) chip GBT-SERDES (“Tape-out” 9th of November) Design/prototype/test of optoelectronics packaging GBTIA + PIN on TO CAN Detailed link specification document (4th Quarter) 2010 Prototype of “complete” GBTX chip Full prototype of optoelectronics packaging 2011 Extensive test and qualification of full link prototypes System demonstrator(s) with use of full link Schedule of the final production version is strongly dependent on the evolution of the LHC upgrade schedule If

26 Additional slides Additional slides Additional slides

27 Power consumption: GBTIA + GBLD + GBTX
PRELIMINARY

28 GBT Link Bandwidth Bandwidth: Dedicated channels: DC balance:
User: 3.36 Gb/s Line: 4.8 Gb/s Dedicated channels: Link control: 80 Mb/s Slow control channel: 80 Mb/s DC balance: Scrambler No bandwidth penalty Forward Error Correction and Frame Synchronization Efficiency: 73% To be compared with 8B/10B: 80% (no error correction capability) Link is bidirectional Link is symmetrical: Down-link highly flexible: (Will be clear later when discussing e-links) Can convey unique data to each frontend device that it is serving “Soft” architecture managed at the control room level Other schemes would require dedicated topologies that will be difficult to accommodate on a generic ASIC like the GBTX Now demonstrated to be compatible with FPGAs

29 Single Event Upsets An issue that needs to be carefully addressed for SLHC links is the expected high rates of Single Event Upsets (SEU). Theses can be caused by: Particle “detection” by Photodiodes used in optical receivers. SEUs on PIN-receivers, Laser-drivers and SERDES circuits First SEU Test results on High Speed Links ( Gb/s) Carried out first survey of results in different devices in Dec.07 12 device types tested PINs without TIA ROSAs with TIA Confirmed that for Error-rates below Error Correction is mandatory Measured Upsets lasting multiple bit periods for the first time

30 Radiation Hard Optical Link Project Collaborators

31 + PFD CP LPF VCO 1/60 Clock reference 1:2 SR 61-bit R 61-bit F
Replica Clock reference rxInputP rxInputN 1:2 SR 61-bit R 61-bit 60 61 rxEvenRegister<60:0> F Phase Detector Half Rate + Coarse tuning control voltage F = 0º F = 90º Sp S0 rxOddRegister<60:0> 1/2 1/5 1/3 rxPhaseInvert rxSkipCycle rxClk160MHz rxClk80MHz rxClk40MHz 2.4GHz 1/3 : 800 MHz 1/2 : 1.2 GHz LSB MSB LSB MSB Shift direction: LSB to MSB D Q


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