1. UVM Based Verification of RISC-V Based Microprocessor Architecture Using System Verilog
Gopakumar.G
Hardware Design Group
Centre for Development of Advanced Computing (C-DAC)

2. Agenda Challenges in Processor Verification
Introduction on UVM based Verification
Strategies for RISC-V Verification using UVM
Stimuli Generation based on layered architecture
Grey box based verification methodology
Assertions for Cycle by Cycle Timing Verification
Register Modeling to Preset Internal States of RISC-V processor
Conclusion

3. Processor Verification : Challenges
Huge functional space of processor architecture
Processor Instruction sets can follow various sequences of occurrences depending on the application program
Processor can also have multiple modes of operations such as addressing modes, read/write hazards etc.
Achieving extensive functional and code coverage
Require extensive controllability on test case generation to create both constrained random and directed test cases at ease
Cycle by cycle verification of Internal register states
Each instruction requires validation of internal registers/memory states on each clock cycle from decode stage until execution stage
State dependent Instruction set validation
Certain instructions during its execution depend on the processor internal states during previous cycles

4. UVM based Verification : Typical Block Diagram
Transaction
A data item which is eventually or directly processed by the DUV
Sequences
A sequence is a series of transaction
Sequencer
Sequencer sends the transaction to driver
Driver
Converts the sequences into meaningful pin level wiggling at the DUV
Monitor
Samples the DUV signals and converts the pin level activity to transaction level
Scoreboard
 Verifies the proper operation of a design at a functional level
Interface
Encapsulates the interconnection and communication between various blocks
Agent
Comprises of the driver, sequencer, and monitor
Environment
Comprises of Agent & Scoreboard

5. RISC V Verification using UVM : Strategies
Stimuli generation through layered architecture for efficient test case generation
Grey box verification methodology for validating the internal states of the processor
Assertions to verify the cycle by cycle timing requirements for each instruction
Register Modeling to preset the internal states of the processor

6. Stimuli Generation: layered architecture
Operation Sequence
The lowest sequence layer
Defines the low level instruction set using basic transactions
Basic transactions comprises of operands, instructions, modes and constraints
Constraints defines the legal scope for each instructions
Constraints Sequence
Generates meaningful set of operations using the required combinations of operation sequences
Constraints defines the required processor operation modes and source/destination addresses for each sequence
Top Sequence
Combination of one or more constraint sequences to generate a meaningful test case.
Can essentially be a full application program or a part of the same

7. Grey box verification methodology: Block Diagram
Interface has access to both the external ports and internal states of the processor architecture
Internal states are accessed using backdoor accessing technique
Eg:
assign reg_bus = RISCV_processor. RISCV_core. register_bus[0];
assign mem_bus = RISCV_processor. memory_bus[0];
Backdoor accessing enables the Monitor block to retrieve the cycle by cycle transitions happening inside the processor

8. Assertions : Cycle by Cycle Timing Verification
Sequence repetition operators and match operators are useful for temporal relationship different processor signals and states
Assertions can be defined in the interface module where all the required bus signals and internal states can be checked for its timing

9. Register Modeling : Preset Processor Internal States
UVM register modeling can be used to configure the internal registers and memory with preset values prior to the execution of a particular instruction
UVM registers employs the backdoor register access method where the internal content of the RISC-V registers and memory can be accessed or deposited using System Verilog Direct Programming Interface (DPI)
The major advantage of backdoor register access over frontdoor access is that the internal state of processor core can mirrored without any delay.

10. Conclusion
UVM based verification accompanied with layered test stimuli generation architecture is one of the most suited verification methodology for extensive verification of RISC-V architecture, since it supports both constrained random stimuli generation and directed test generation
Validation of the internal states of the RISC-V processor for each clock cycle can be achieved using the backdoor accessing of the internal registers and memory.
The verification/debugging turn around time of the RISC-V processor can be considerably reduced by configuring the internal states of the processor with preset values through register modeling

11. References
S. Rosenberg, M. A. Kathleen, “A Practical Guide to Adopting the Universal Verification Methodology (UVM)”, Cadence Design Systems, 2010.
Mustafa Khairallah, " Reusable Processor Verification Methodology Based on UVM," DVCON Europe, 2014
Andra Radu, “System Verilog assertion verification with SVA Unit,” DVCON US, 2016
Andrew Waterman, The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1
A. Piziali, “Verification Planning to Functional Closure of Processor-Based SoCs,” Incisive Verification Article, Cadence Design Systems, May 2006.
C. Spear, “System Verilog for Verification, A Guide to Learning the Testbench Language Features,” Springer, 2008.
Mentor Verification Academy (UVM Cookbook, Training Videos)

12. Bio
Myself, Gopakumar.G serving as senior engineer in Centre for Development of Advanced Computing (C-DAC) since January I have got more than 10 years of experience in ASIC Physical Design in deep submicron technologies and UVM based Verification IP development. I have successfully completed two multimillion gate ASICs tape-outs in 130nm technology node and 4 UVM based verification IP designs in C-DAC. Prior joining C-DAC I have been working as design engineer in Fujitsu ODC under NEST, where I participated in the tape-outs of ADC/DACs in 90nm and 65nm technology nodes. I have filed 4 Indian patents and 1 US patent . I hold a bachelor degree in Electronics and Communication Engineering from University of Kerala.