1. Introduction to Vivado Design Suite

2. Vivado Design Suite
Vivado is the new tool that only supports 7 series FPGA, UltraScale and all more recent families.
Completely re-developed from scratch
The algorithms for Vivado are implemented with having the ever-growing size of FPGAs in mind
New deterministic Place and Route Algorithm
All steps have the same view on a global data structure
Vivado HLS: High-level sysnthesis tool
Xilinx Design Constraints
All tools in Vivado except SDK and Vivado HLS are integrated part of the GUI

3. ISE Vivado New integrated GUI All tools in Vivado except
SDK and Vivado HLS are
integrated part of the GUI

4. Vivado GUI

5. Creating a new project

6. Project manager

7. IP Integrator

8. Simulation: create testbench

9. Simulation: edit testbench

10. Running simulation

11. Specifying constraints: Specifying constraints
XDC Consttraints (replacement of UCF)
XDC constraints are a combination of:
Industry standard Synopsys Design Constraints (SDC), and
Xilinx proprietary physical constraints
XDC constraints have the following properties:
They are not simple strings, but are commands that follow the Tcl semantic.
They can be interpreted like any other Tcl command by the Vivado Tcl interpreter.
They are read in and parsed sequentially the same as other Tcl commands.

12. UCF to XDC
Source: Vivado Design Suite Migration Methodology Guide (UG911) p 23

13. Creating or adding XDC file

14. Creating XDC file

15. Master XDC

16. Design elaboration: I/O Planning

17. Design elaboration

18. Synthesis and the synthesized design

19. Implementation and the implemented design

20. Reports

21. Generating bitstream

22. Hardware manager: open target

23. Hardware manager: open target

24. Hardware manager: program device

25. Questions?