1. Wafer bonding (Chapter 17) & CMP (Chapter 16)

2. Wafer bonding applications
Advanced substrates (SOI)
Packaging
Capping/Encapsulation
Multi layer devices
3D structures
Layer transfer
Wire bonding
Flip chip bonding
Not part of this course

3. Wafer bonding techniques
direct bonding: Si/Si, glass/glass, PMMA/PMMA,…
  also known as fusion bonding
anodic bonding (AB): Si/glass, glass/Si/glass 
thermo-compression bonding (TCB): Au-Au
eutectic bonding: Si/Au (363oC)
glass frit bonding: glass melting  
adhesive bonding: “glues” applied, any substrate

4. Basic requirements for bonding
Wafers are flat (no centimeter scale wavyness)
Wafer are smooth (atomic/micrometer scale)
Materials form chemical bonds across interface
High stresses are avoided
No interface bubbles develop

5. Bonding process steps -particle removal
-surface chemistry modification
-(optional) vacuum pumping
-(optional) wafer alignment
-room temperature joining
-application of force/heat/voltage
-(optional) wafer thinning

6. SOI wafer fabrication: bonding an oxidized wafer to a bare silicon wafer
device Si
BOX
Handle Si
a) surface preparation
b) room temperature joining
c) annealing for bond improvement d) top wafer thinning
BOX= buried oxide

7. Why SOI wafers ? CMOS Why not SOI ? Expensive MEMS
-easy isolation of transistors
-fewer process steps
-elimination of substrate effects
 faster transistors
-easy etch stop
-single crystal material superior
-device and handle silicon optimized separately
Why not SOI ? Expensive

8. Bonding = chemical bonds form across the interface
At low temperature:
weak hydrogen bonds
At high temperature:
strong Si-O-Si bonds
Tong & Gösele: Semiconductor wafer bonding

9. Bond strength
Tong & Gösele: Semiconductor wafer bonding

10. Silicon fusion bonding: cMUT (capacitive micromachined ultrasonic transducer)
SOI wafer
Processed bulk wafer
Etching away SOI handle and BOX
Processing electrodes on the device SOI membrane
Yongli Huang, JMEMS 2003, p. 128

11. Anodic bonding: Si-glass
At elevated temperature Na+ ions in glass become mobile
Electric field drives Na+ towards cathode
Oxygen O- ions in glass migrate towards silicon anode
Depletion region
High electric field
Attraction of wafers

12. Anodic bonding: Si-glass
Double Sided Heating:
High Voltage:
Bonding Atmosphere:
e.g. 350°C
e.g. 500V
e.g. 1 mbar nitrogen

13. Thermal matching Si-glass
Coefficients of thermal expansion of silicon and glass must be matching, otherwise cracking upon cooling
 only certain glasses suitable for anodic bonding: Pyrex, Borofloat

14. Anodic bonding: capacitor
Silicon DRIE etched
Al capacitor electrode
Al counter electrode on a glass wafer
Materials must tolerate ca. 400oC
Accurate gap control because no intermediate materials

15. Glass-silicon-glass anodic bonding
Fig. 1.10: Oxyhydrogen burner of a flame ionization detector by Pyrex-glass/silicon/Pyrex-glass bonding, from ref. Zimmermann 2002.

16. Adhesive bonding photoresists (spin coated, photopatterned)
glues (e.g. silk screen printing)
Applicable to almost any material
If thick photoresist used, not sensitive to particles
Temperatures oC (resists are polymers !)

17. Adhesive bonding (2)
Because of low temperature, CMOS electronics not affected
Spin coating determined thickness (and actuation voltage)

18. Bond alignment None Perfect Misaligned Simple equipment enough
Requires advanced tools
Misaligned
Some devices more sensitive to misalignment than others.

19. Bond alignment (2)
Critical alignment
Non-critical alignment

20. CMP: Chemical-Mechanical Polishing
Chemical Mechanical Polishing (CMP) combines chemical action with mechanical abrasion to achieve selective material removal through polishing
Microfabrication

21. Applications of polishing
Smoothing
Planarization
Damascene
SiO2 Cu Al

22. Applications of polishing
Smoothing
Planarization
Damascene
SiO2 Cu Al

23. Applications of polishing
Smoothing
Planarization
Damascene
SiO2 Cu Al

24. Cu damascene vs. W etchback ?
CMP
etching

25. Results of CMP Planarization Polishing SiC wafer before and after CMP
CMP of SiO2
Planarization
Polishing
Microfabrication

26. Rotary CMP tool
60-90s per wafer

27. Polishing in action
Polishing pad

28. Grinding vs. polishing 500 µm 10 µm Both use abrasive particles, but:
Grinding removes 10 µm/min in large chunks because large particles
Grinding results in very rough surface because very large chunks
Grinding leaves mechanical damage due to large chunks being torn off
Polishing uses nanoparticles to achieve smooth surfaces
Polishing removes 0.1 µm/min because small particles, small forces
Mechanism of removal is chemical and mechanical (CMP !)

29. Polishing needed after grinding !
Planarization
Damascene
SiO2 Cu Al
Surface roughness e.g. 200 nm
CMP
Surface roughness e.g. 1 nm

30. Erosion and dishing in CMP
Pattern density dependent
Size dependent
Material softness dependent

31. Photonic crystal by CMP

32. Log pile photonic crystal fabrication
Poly-Si
Si wafer
CVD of oxide
CMP of oxide
CVD of poly-Si
oxide

33. Poly-Si litho & etching
CVD of poly-Si
CVD of oxide
CMP of oxide

34. Etch all CVD oxide away with HF