1. 3-bit threshold adjustment
SKIROC
The last prototype of a front-end chip for silicon pin diode read-out dedicated to the Si-W ECAL for ILC
Michel Bouchel, Frederic Dulucq, Julien Fleury, Christophe de La Taille, Gisèle Martin, Ludovic Raux, Nathalie Seguin, Omega / LAL /IN2P3
Mowafak El Berni, Francois Wicek, LAL/IN2P3
Gérard Bohner, Jacques Lecoq, Samuel Manen, Laurent Royer, LPCC/ IN2P3
Introduction
SKIROC (standing for Silicon Kalorimeter Integrated read-Out Chip) has been designed to read out the upcoming W-Si electromagnetic calorimeter technologic prototype. That new generation calorimeter is developed by the Calice collaboration and the EUDET European research program. The aim of that prototype is to validate the feasibility of a full-scale high-granularity ECAL for the international linear collider. Expectations on the front-end electronics are cutting edge to achieve the required integration, compacity and uniformity of calorimetric measurement on 82 millions of channels.
Compacity, integration : It is necessary for such a high number of channel to have the front-end electronic as close as possible to the detector to minimize the lines and cables that introduce noise through a parasitic capacitance. The feasibility of the calorimeter is involved by the ability to embed the front-end ASIC inside the calorimeter. Meanwhile, the dead material shall be minimized and a cooling system inside the calorimeter would degrade the physics performance. It is therefore necessary to achieve a ultra-low power consumption to avoid active cooling. The ILC beam structure combined with a power pulsing capability implemented in the front-end ASIC allow to reach the beyond-state-of-the-art consumption of 25µW/channel (including ADC and buffer to DAQ).
Number of channels, performances : Calorimetric measurement requires a 15 bit resolution. The 12 bit wilkinson ADC combined with the dual shaper embedded in SKIROC ensure a 15.3 bit resolution. To keep the data flow to the DAQ acceptable, a zero-suppress associated to an internal trigger has been included to convert and output only valid data ( e.g. above an adjustable threshold). That channel by channel self trigger associated with the very low occupancy of the detector allow a data reduction of 104 making the data rate acceptable within the tight power budget.
Front-end PCB
SKIROC
PCB
WAFER Si
PCB – FRONT
PCB – BACK
The technologic prototype :
A tungsten-carbon fiber structure
Detector slabs, hosting silicon wafer and front-end electronic slid in the structure
Aluminium shield
Copper radiator
Front-end ASIC
Si Wafer
W-Carbon fiber H structure
The ASU (Active Sensor Unit) :
Each detector slab is composed of several Active Sensor Unit (ASU) stitched together
An ASU is a ultra-thin PCB hosting Si Wafers on one side and VFE electronic on the other
W- C. fiber
Structure
Detector slab
An ASU (Active Sensor Unit)
VFE ASIC bonded in a PCB
Artist view cut of a VFE ASIC bonded in a PCB
ASU stitching
To ensure such a high integration, the VFE ASIC :
Run autonomously
Don’t need external component
No bias resistor
No decoupling capacitance
No matching component
Characteristics
Designed for 5*5 mm² pads
36 channels
Detector AC/DC coupled
Auto-trigger
MIP/noise ratio on trigger channel : 16
2 gains / 12 bit ADC  2000 MIP
MIP/noise ratio : 11
Power pulsing (Programmable stage by stage)
Calibration injection capacitance
Embedded bandgap for references
Embedded DAC for trig threshold
Compatible with physics proto DAQ
Serial analogue output
External “force trigger”
Probe bus for debug
24 bits Bunch Crossing ID*
SRAM with data formatting*
Output & control with daisy-chain*
Ch. 0
Ch. 1
Analog channel
Analog mem.
Ch. 35
Bunch crossing
24 bit counter
Time
digital mem.
Event
builder
Memory
pointer
Main
SRAM
Com
module
ECAL SLAB
*digital part are implemented in a FPGA in the first version of the ASIC
36-channel
Wilkinson
ADC
Trigger
control
ADC performance 1V
0.125V
NonLinearity (mV)
Performance (simulated):
Resolution: 12 bits
Consumption: 3 mW
Conversion time: 80 µs 50MHz)
Integrated cons.: (3mW * 80µs)/200ms= 1.2µW
Current source (ramp generator):
Input dynamic signal: 1V Common Mode
2V differential ramp generator
T° sensitivity : 40 ppm/°C max (20 to 50°C)
Power supply sensitivity: 5 ppm/°C (±50 mV)
NonLinearity (simulated):
< ± 500 µV up to 125mV
< 0.1% from 125mV to 1V
One channel layout
System behaviour
time
Time between two trains: 200ms (5 Hz)
Time between two bunch crossing: 337 ns
Train length bunch X (950 us)
Acquisition
1ms (.5%)
A/D conv.
.5ms (.25%)
DAQ
1% duty cycle
IDLE MODE
99% off
199ms (99%)
ILC beam structure and front-end chip operating mode
A/D conversion
When an event occur :
Charge is stored in analogue memory
Time is stored in digital (Bunch crossing ID) memory
Trigger is automatically rearmed at next bunch crossing ID
Depht of memory is 5 and will be extended to 16 in next version
The data (charge) stored in the analogue memory are sequentially converted in digital and stored in a SRAM.
An event in RAM is :
The Bunch Crossing ID
The charge
The shaper gain
The status of the trigger
The events stored in the RAM are outputted through a serial link when the chip gets the token allowing the data transmission.
When the transmission is done, the token is transferred to the next chip.
256 chips can be read out through one serial link
Slab FE
FPGA
PHY
VFE
ASIC
Data
Clock+Config+Control
Conf/
Clock
Front-end chip operating mode description
Multi-chip connexion in a slab
The system on chip has been designed to fit the ILC beam structure. The valid data are stored in each front-end chip during the beam train. The data are then converted in digital and sent to DAQ during the inter-train. When all these operations are done, the chip goes to idle mode to save power.
Analogue channel 50 1
0.4pF
0.8pF
1.6pF
3.2pF
1pF
2pF
4pF IN
OUT
20M 1M
200ns
G=10
G=1
Analog Memory
Depth = 5
G=100
G=5
12 bits
ADC
Gain selection
06pF
3-bit threshold adjustment
10-bit DAC
Common to the 36Channels
100ns
DAC output Q
HOLD
Preamp
Ampli
Slow Shaper
Fast Shaper
Trigger
Charge measurement
3pF
Calibration input
input
Low noise – variable gain charge preamplifier
Slow control selectable calibration injection capacitance
High gain fast shaper + discriminator for trigger line
Dual shaper and SCA for charge measurement
12 bit wilkinson ADC
10 bit DAC for trigger threshold adjustment
One channel block scheme
Preamplifier schematic
LAL and Omega
LAL (Laboratoire de l’accélérateur linéaire) is a physics laboratory in Orsay (France), 20 km south from Paris. 350 people including around 100 physicists work on many experiment in cosmology, high energy particle physics and accelerator. Several technology group such as the mechanic or the electronic group work on applications to achieve physicist expectations.
The LAL electronic group (50 people) is divided in 3 units : system unit, microelectronic unit, and test unit. Teams are involved in many big physics experiments such as Atlas, Planck, Auger and ILC. The group can work on project from the manufacturing standard to the production and ensure maintenance.
The microelectronic team has acquired a sharp knowledge in full-custom analog ASIC design. Its specialization is focused on low-noise high-speed front-end chip and on high-precision calibration devices. Its know-how is evolving to system-on-chip designs that embed front-end electronic, auto-trigger system, calibration devices and digital converter.
IN2P3 (Nuclear and particle physics French institute) has recently asked for a rationalization of engineering resources in microelectronic and is building competence poles. Omega is the pilot structure. 10 engineers are currently in the Omega team, ensuring the R&D of several complex chip per year to serve particle physics.