1. Objective of the Meeting
Consolidating the necessary platform to perform experiments of common Japanese-IRFU – MINOS, ACTAR, MUST2 …
Mount an active exchange program between IRFU and Japanese institutions through RIKEN and with RIKEN in the domains of detection and electronic data collection.
In view of:-
Participating in developing a new high bandwidth, large dynamic range and channel number daq systems for the Nucl. Phys. community. Exchange of Students/Post Doc. In view of samuraï
Building of shared expertise to enhance the use of highly segmented gas amplifiers at RIKEN .

2. Possible use of GET @ RIKEN
Emanuel Pollacco
For GET Collaborations

3. A possible Plan Schedule of GET.
General comments about future experiments at RIKEN.
A walk around MUTANT+BEM

4. Emanuel Pollacco IRFU/SPhN
For the GET collaboration

5. Objectives of the GET Project
Develop Front-End Electronics and Data Acquisition system for Active Targets tailered for the Nuclear Physics requirements.
Low detection thresholds & High Luminosity
Require:
Internal versatile TPC Trigger
High: dynamic range (~Z²), bandwidth, channel density
Opportunity to develop a generic/reconfigurable approach for Nucl. Phys. to cover medium size systems.
Emanuel Pollacco IRFU/SPhN

6. Systems to be covered by GET
Projects employing GET
ACTAR ( GANIL, IRFU, IPNO, SFTC, …) – Micromegas + Si – 20k channels
2p-TPC (CENBG) – GEM/Micromegas – 20k channels
AT-TPC (MSU, LBL …) – Micromegas – 12k channels
GASPARD (GANIL, IRFU, IPNO, ... ) – Si & CsI – 15k channels
BTD (IRFU & GANIL) – 100 channels
Under Study
S3 – (SPIRAL2) – Si channels
SAMÜRAI-TPC (RIKEN) – Micromegas -15k channels
MINOS  (p;2p, g) (IRFU)
FISSION-TPC (IRFU) - Micromegas
Emanuel Pollacco IRFU/SPhN

7. SYSTEM GET Conceptual Design (6 Hardware elements)
Possible derivatives – see Eric & Shebli
µ-TCA
AsAdASIC
ADC
FPGA
PULSER
T/V/I
CoBo
FPGA
PAC
Mutant
Trigger
FPGA
ACTAR 1
Emanuel Pollacco IRFU/SPhN

8. Reconfigurable Approach
Via:- Hardware & Software Architecture
(Documentation & Simulation tools
Multi-lab Multi-project collaboration)
µ-TCA
AsAdASIC
ADC
FPGA
PULSER
T/V/I
CoBo
FPGA
PAC
Mutant
Trigger
FPGA
Slow Control Software (Data Base Driven)
Ext/Int Control Web Serv.
Evolutive Data Formats
Software Development /Debbuging Tools
NARVAL for data managment
Emanuel Pollacco IRFU/SPhN

9. MUST2-ASIC Engy/Time or AGET Shape/Time GASISIPLEX AGASP … ?
ASIC-A&N
MUST2-ASIC
Engy/Time or
AGET
Shape/Time
GASISIPLEX
AGASP … ?
FPGA
Temp, V, I, Cont.
Slow-Cont. Interf.
Front -End
ADC
Cooling
Power
Back –End
Collector
Slow.Cont.
FPGA.
Fast Switch
PC-Farm
Fast Memory 30
PAC
AsAdASIC
ADC
PULSER
FPGA
T/V/I
µ-TCA
CoBo
Mutant
Trigger 1
Trigger
Time.Stamp
FPGA.
Fast Memory 3

10. µ-VME system MUST2 MUST 2 ~ 2000ch 8 Telescopes = 8X 100cm²
256 DSSD E & T
E 20KeV / T 300ps FWHM
16 ch Si(Li)
16 ch CsI
Pulser PA+Amp+
Disc +TAC+multiplex in Vac

11. MUST2 Vacuum Cooling Unit Power supply V M E Security AUTOMAT Current
Tension
Temperature
Pressure
Vacuum
Cooling
Unit
Power supply S L O T G M T U 2 M C E N T R U M M U V I M U V I V M E

12. MUSETT COFEE board (64 strips) IPNO ATHED ASIC (16 strips E + T,
36 mm2, slow controlled)
DSSD 10x10 cm2
strips
300 μm
Windowless
Resolution ~ 30 keV
Detector module
(with front-end
electronics, cooling)
Christophe THEISEN - EURORIB 2010

13. GET Shedule Conceptual Design R&D Testing Procedures Production
HARDWARE (32,000 channels)
SOFTWARE
Testing Procedures
Production

14. GET Schedule Conceptual Design R&D Testing Procedures
ASIC-A&N
Conceptual Design
R&D
HARDWARE (32,000 channels)
Front-end card – PCB – AsAd - 120
Analogical-Numeric ASIC - 480
Numeric – ASIC: FPGA - FIRMWARE
ADC
Back-end card – PCB – CoBo - 30
Numeric – ASIC: FPGA – FIRMWARE
Fast Memory
Back-end card – PCB – Mutant - 3
Numeric – ASIC: FPGA-1 – FIRMWARE
Numeric – ASIC: FPGA-2 – FIRMWARE
µ-TCA - 3
Switch
PC-Farm - 6
SOFTWARE
Data acquisition management (NARVAL)
Slow Control
Testing Procedures
Production (~max)
3000 AGET, 300AsAd, 80CoBo,
FPGA
Temp, V, I, Cont.
Slow-Cont. Interf.
AsAd
ADC
Cooling
CoBo
AsAd
Power
MuTant
FPGA.
Fast Memory
CoBo
FPGA.
MuTant
FPGA.

15. Schedule for GET

16. What would make us reach-out from the VME universe to the µ2 universe?
Number of channels
Bandwidth
Uniformity in the system building
Need to launch-off from the VME based instrumentation
Student support!

17. Beam
Tracking
VME
Time-Stamp
MINOS µ2
Time-Stamp µ2
Time-Stamp
DALI2/
SHOGUN
VME
Time-Stamp
Neutron-Wall
VME
Time-Stamp
SHARAQ
µ-VME
Time-Stamp

18. Beam
Tracking
VME
Time-Stamp
ACTAR µ2
Time-Stamp
MUST2
µ-VXI
Time-Stamp
SHARAQ
µ-VME
Time-Stamp

19. Beam
Tracking
VME
Time-Stamp
2p-TPC µ2
Time-Stamp

20. Beam
Tracking
VME
Time-Stamp µ2
Time-Stamp
SAMURAÏ
TPC µ2
Time-Stamp
Si-Wall
VME
Time-Stamp
Event
Building
CPU-Farm
Storage
Neutron-Wall
VME
Time-Stamp

21. MuTanT 3 Levels of Trigger: -LØ= External Trigger
-L1 = Multiplicity Trigger
-L2 = Hit Pattern Trigger
Gilles W
(GET L2 TRIGGER – PHYSICS SCENARIOS GANIL-DEC09)

22. Continuity check Level 2 = Hit Pattern Trigger
Figure 3. Example of an ensemble of contiguous pads defining a track.
Figure 3. Example of an ensemble of contiguous pads defining a track.
Figure 3. Example of an ensemble of contiguous pads defining a track.
Figure 3. Example of an ensemble of contiguous pads defining a track.
Figure 3. Example of an ensemble of contiguous pads defining a track.
Figure 3. Example of an ensemble of contiguous pads defining a track.
Figure 3. Example of an ensemble of contiguous pads defining a track.
Level 2 = Hit Pattern Trigger
Continuity check
Example of an ensemble of contiguous pads defining a track
A track may be defined by a minimum number of continuous blocks
Block size is important:
- smaller block size = more efficient selection
( higher throughput …)
- but more processing = more dead time

23. Origin check Level 2 = Hit Pattern Trigger
No valid blocks (=1) to the beam projection,
The event is classified as a pure beam event
and is accepted
Some valid blocks (=1) are present at different
position along the beam projection, the event
is rejected

24. Level 2 = Hit Pattern Trigger
Isolated group of macropads have to be checked
to know if it’s a fragment of a track
The two possible lines do not cross valid blocks
Event rejected
A straight line could be defined by
the two extreme blocks (in red)
taking into account their coordinates
The lines cross valid blocks
Event accepted

25. MUTANT A 3- Level Numerical Trigger Event TPC Multiplicity Hit Pattern
Y/N
Event TPC
Multiplicity
Hit Pattern
Event TPC
Multiplicity -
Level #1
Trigger
Y/N
Ext to
GET
Event TPC -
Hit Pattern
Level #2
Trigger
Y/N
Event TPC
ADC Read
Calculated
Hit Patten
Data In
Farm
Data In
GET
Zero Remove
Time Stamping
Formating
Data In
GET
Level # 3
Event-Building
Data Reduction

26. Coding of TRIGGER Model Based Testing
Level # 0
~ 0 ns
Level # 1
~ 300 ns
Level # 2
~70µs
40ns/sample
Max/Channel 40X512ns
=20µs
Max/AGET
40X512X64ns
=1.3ms
Coding of
TRIGGER
Model Based
Testing

27. BEM
Vadatech µ-TCA

28. Coupling 2 or more µ2 systems
Back –End
Collector
Slow.Cont.
ASIC-N - FPGA.
Fast Switch
Fast Memory 5
Trigger
Master
Time.Stamp
ASIC-N - FPGA.
Fast Memory 1
PC-Farm
Storage
Trigger
Time.Stamp
ASIC-N - FPGA.
Fast Memory 3
Back –End
Collector
Slow.Cont.
ASIC-N - FPGA.
Fast Switch
Fast Memory 30
Coupling 2 or more µ2 systems

29. EMC, Connectors, Cables, Monitoring, Testing & Security
Cooling Study
CEM Study
µ-TCA
AsAdASIC
ADC
FPGA
PULSER
T/V/I
CoBo
FPGA
Mutant
Trigger
FPGA
SAMÜRAI -TPC
Power Supplies
Power
SPY-BOX
Emanuel Pollacco IRFU/SPhN

30. MUST2 – ASIC MATE