1. CLUster TIMing Electronics Part II
Luigi Cappelli
on behalf of CLUTIM group
SuperB Workshop - LNF – 4 April 2011

2. Outline ADC output signal CLUTIM aims Device Selection (Virtex 5 vs 6)
Virtex 6 Layout
ISE Development Enviroment
VHDL Algorithm
FFT Test
Future Planning
SuperB Workshop - LNF – 4 April 2011

3. 12 bit (6+6) discretized signal 500 MHz frequency LVDS bus
ADC output signal
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
The input signal of our electronics is the signal coming from the ADC; A typical real event is shown in this figure. As you can see in the picture and as it has been previously shown, it is a 12 bits discretized signal made by 2 parallel event, 6 bits each, with a frequency of 500 MHz and a LVDS standard.
12 bit (6+6) discretized signal
500 MHz frequency
LVDS bus
SuperB Workshop - LNF – 4 April 2011

4. CLUsterTIMing aims Read & Store Data coming from ADC: Peak Detection
MAX
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
AMPL ∆T
Read & Store Data coming from ADC:
Peak Detection
Amplitude and Timing Peak Information Storage
The aims of our electronics is principally to detect all the significant peak of the discretized signal, to store the needed information as amplitude, timing and event number.
SuperB Workshop - LNF – 4 April 2011

5. Virtex 6 ML605 Evaluation Kit FMC Connector
Device Selection
Virtex 6
ML605 Evaluation Kit
FMC Connector
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
So we moved to a ML605 Evaluation Kit. As you can see in the datasheet, the maximum input clock frequency is equal to 710 MHz, more than what we needed. Moreover a different kind of connector it’s implemented, FMC connectors.
SuperB Workshop - LNF – 4 April 2011

6. ML605 Evaluation Kit VITA 57.1 FMC LPC Connector Up to 700 MHz
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
VITA 57.1 FMC LPC Connector
Up to 700 MHz
No coupling problems
As it’s shown, the different shape of the connector doesn’t give significant coupling problems, so the clock has no significant frequency limitations.
SuperB Workshop - LNF – 4 April 2011

7. VITA 57.1 FMC LPC Connector 12 differential inputs
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
12 differential inputs
1 differential clock input
This is the FMC connector layout. We need 12 differential inputs coming from the ADC and a differential input line for the clock. The highlighted ones are the pins who are used.
SuperB Workshop - LNF – 4 April 2011

8. Possible Setup Possible direct coupling Using a daughter board
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
Possible direct coupling
Using a daughter board
Gandalf Experiment
Moreover, to avoid unwanted coupling effect, a possible direct coupling strategy can be used. The connection can be made using a daughter board, as shown in figure. This pictures comes from Gandalf Experiment, made by INFN of Trieste.
SuperB Workshop - LNF – 4 April 2011

9. Developing Setup Use of a daughter board to connect ADC to Virtex 6
FMC
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
BSH
Particulary, the idea is to create two daughter boards to have the possibility to connect the ADC board to the Virtex 6 Kit using the mentioned FMC connectors, and to connect the ADC to a logical analyzer using a different connector, in particular a BSH connector, in order to test the third version of the chip before coupling it with the Virtex board.
Use of a daughter board to connect ADC to Virtex 6
Use of another daughter board to connect ADC to Logical Analyzer
SuperB Workshop - LNF – 4 April 2011

10. Possible Setup – Daughter Board
VITA FMC Connector
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
BSH Connector
This is the developed layout of the daughter board that allow us to connect the ADC with the Virtex 6. Particulary you can see, on the upper part, the footprint of the FMC Connector going to Virtex and, on the lower part, the BSH Connector going to ADC board. Of course, to match the impedance, ground planes have been created.
Use of a daughter board to connect ADC to Virtex 6
Impedance Matching
SuperB Workshop - LNF – 4 April 2011

11. ISE Development Enviroment
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
Version 12.4
HDL-Based Design
Behavioral Simulation
Timing Simulation
Constraints
Let’s pass now to the software. The used development enviroment is Xilinx ISE. A HDL based design has been developed, with behavioral simulation. Timing simulation and constraints are the next step to be done.
SuperB Workshop - LNF – 4 April 2011

12. VHDL Algorithm Overview
ADC Signal
2 or 3 points average
Smoothing
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
2° derivative AND Sign
Derivative & Sign Condition
Max values storage in memory
Max Detection
The VHDL algorithm follows the shown diagram. The ADC signal needs to be smoothed to better filter noise, and the algorithm allow us to select different kind of smoothing, calculating the average on 2 or 3 points. After the smoothing a series of operations and calculations are made, derivative and sign calculation, in order to find the local maximum value. Once the max is detected it is stored and the enable signal is given to the time counter in order to have timing information. The event time window duration can be set, once the time window counter expires, the end counter flag is set to start taking a new event.
Enable Signal
Time Counter
End Counter Flag
Time Window End
SuperB Workshop - LNF – 4 April 2011

13. VHDL Algorithm – Behavioral Simulation
ADC
Smoothing
Enable
Max Reg
Counter
This is the result of a behavioral Simulation. As you can see the ADC incoming signal are firstly smoothed, then, when a peak is detected, the relative enable signal is set, the max register store the information, and the counter starts to count. Once the time window flag will set the end of the event, timing information will be stored as well.
From data point of view, data flow is like a pipeline structure. At the end of the developing process, the storage will be made using a FIFO.
Concerning noise evaluation, the selection of a baseline will depend on the ADC signal.
Smoothing tuning
Max Register
Enable counter
End counter
SuperB Workshop - LNF – 4 April 2011

14. VHDL Algorithm – Counter
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
Here you can see a screenshot of the counter algorithm. As we’ve previously seen, it is triggered by the enable signal, in this case from Enable0, and it will count till the end of time window giving us timing information.
Triggered by Enable signal
It gives peak timing information
SuperB Workshop - LNF – 4 April 2011

15. VHDL Algorithm – Timeout
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
This is, instead, the time window timeout code. Everytime a peak is detected, the timeout counter is reset. Once it reached the end set value, a flag is used to move to the next event.
It gives the end of the event
It is reset by rst_tout signal that is set when a peak is found
End_counter flag
SuperB Workshop - LNF – 4 April 2011

16. FFT Check Algorithm FFT with input signal frequency 500 MHz
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
In order to check if the signal coming from the ADC and the one entering the Virtex 6 board has no distorsion, due to coupling capacitance of the connectors or other kind of distorsions, a FFT analysis will be carried out. The test signal will cover the desired frequency range, around 500 MHz.
FFT with input signal frequency 500 MHz
ADC Output Signal vs Virtex 6 Input Signal
Find potential signal distortions
SuperB Workshop - LNF – 4 April 2011

17. State of the art III Version of ADC chip developed
VHDL code improvement in progress
Timing Simulation
Constraints
FFT Readout algorithm in progress
Daughter boards layout ready, waiting for realization
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
So, concerning the “state of the art” of our work: the third version of the ADC chio has been developed and needs to be tested. VHDL code improvements and simulation using constraints are in progress. The FFT readout algorithm will be made as soon as the daughter boards will be ready.
SuperB Workshop - LNF – 4 April 2011

18. Future planning...
Once the entire chain (ADC + Virtex) will be tested and the VHDL code will be optimized we think to realize a VME board in order to read up to 4 ADC channels.
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
Finally the future plans are to realize a VME board in order to read up to 4 ADC channels.
SuperB Workshop - LNF – 4 April 2011

19. Thank you for your attention
SuperB Workshop - LNF – 4 April 2011

20. Backup Slides SuperB Workshop - LNF – 4 April 2011 ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
SuperB Workshop - LNF – 4 April 2011

21. Abstract
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
A Cluster Timing Algorithm has been developed in order to store information coming from the 500 MHz ADC signal. In particular the algorithm detect signal peaks, storing their amplitude and timing information. A Xilinx ML605 Evaluation Board has been used in order to develop and test the VHDL code, using a FPGA Virtex 6 chip. The final goal is to develop a VME board in order to read up to 4 ADC channels. Code improvements are currently being evaluated.
SuperB Workshop - LNF – 4 April 2011

22. Il BUS di espansione Dip. di Fisica
SuperB Workshop - LNF – 4 April 2011

23. SuperB Workshop - LNF – 4 April 2011

24. Virtex 5 initially selected ML50X Family
Device Selection
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
Virtex 5 initially selected
ML50X Family
In order to start the development of the algorithm we had to select the best development device. Initially a Xilinx Virtex 5 FPGA chip with ML505 Test board was chosen. As you can see, from the datasheet information, the clock frequency is supposted to be up to 550 MHz, suitable for our application.
SuperB Workshop - LNF – 4 April 2011

25. Previous experimental experiences led to different solution
ADC output
CLUTIM aims
Device Sel.
Virtex 6
ISE 12.4
VHDL code
FFT Test
Future Plans
Previous experimental experiences led to different solution
Pins coupling problems
( Frequency limitation due to parasitic capacitance )
But if we see the physical characteristic of the shown evaluation platform, in particular the pin connector, a problem comes up. Infact, previous experimental experiences, led to different solution since coupling problems have been found. Because of the shape of those pins, the effect of parasitic capacitance reduces the bandwith of the incoming signal, creating a frequency limitation not compatible with our target. Then we had to move to a different board and we choose a Virtex 6 FPGA chip.
SuperB Workshop - LNF – 4 April 2011