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Status on development of a White Rabbit Core
P.P.M. Jansweijer, H.Z. Peek
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Spartan-6 (SP605)
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Master/Slave test setup block diagram
Bidirectional Loopback the recovered clock @ 1.25 Gbps conform standard IEEE 802.3 (1000BASE-X, Gigabit Ethernet) Master Slave TxUsrClk RxUsrClk Tx Rx Start Slave BitSlide SFP SFP Stop Rx Tx RxUsrClk Master BitSlide TxUsrClk Master + Slave BitSlide For details please see Technical Report “ETR ”:
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Spartan-6 Test setup Using two SP605 Evaluation Platforms 10 Km fiber
(XC6SLX45T‐3FGG484CES) Clock Loopback (DPLL) Stop Stop DAC Start Master VCXO Slave
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Resynchronization in action
3 1 RxRecClk BitSlide(4:0) Unit Interval (UI) = 1 = 3 = 0 Start/Stop delay Algorithm: Propagation Delay = “Start-Stop” Delay + “LED Value” * UI
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FPGA SerDes remarks The Receiver Deserializer should provide a means to (manually control) “Bit Slip”. Tested in: Family SerDes Name Bit Slip Test Remark Xilinx Virtex-5 GTX RxSlide Okay GTP +/- 1 UI Xilinx ug196 Table E-2 Spartan-6 Rx_BitSlip Virtex-6 ? Altera Stratix-IV-GX GXB Lattice SC/M FlexiPCS x Fail
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SP605 FMC connector debug LEDs
Master Slave PLL_LockDetect PLL_LockDetect RxInSync RxInSync TxRxLocked 4 3 Master + Slave BitSlide (4..0) Slave BitSlide (3..0)
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XC6SLX45T GTP Clock configuration issue
Okay Okay RefClk RefClk GTPA1_DUAL_X0Y0 GTPA1_DUAL_X1Y0 FAIL Okay RefClk RefClk GTPA1_DUAL_X0Y0 GTPA1_DUAL_X1Y0 Prevents fibre (SFP) implemenation + SMA Clock Input (needed for VCXO) on SP605 Place & Route software bug? Silicon bug? Engineering sample/production device? => Xilinx Web Case
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Spartan-6 Test setup via SMA
Stop Start X4 X4: a few hundred ppm of target frequency C324/C325 Using two SP605 Evaluation Platforms Master Clock Loopback (DPLL) SMA Cables DAC Slave VCXO
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WR Core block diagram (Slave)
“The Ugly Switch Endpoint Diagram” MAC Address Filter GMII t1, t4 RXD<7:0> SFD Detect Receive Engine RX_ER Rx Fifo RX_DV RX_CLK PHY (GTP) 802.3bf gRS Flow Control VCXO SFP Client Interface GTX_CLK TXD<7:0> Transmit Engine TX_EN Tx Fifo (may be software) Client TX_ER SFD Detect Management Configuration 72 SYSTIM Time Stamp BitSlide 5 t2, t3 RXSTMPH/L (t2) TXSTMPH/L (t3) RXSATR H/L SourceID/SequenceID
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Interesting literature
INTEL datasheet Quad Gigabit Ethernet LAN + PTP Controller Chapter 7.9: “Time SYNC” IEEE 802.1AS defines protocol and procedures for the transport of timing over Bridged and Virtual Bridged LAN IEEE802.3bf defines the Time Synchronization Service Interface (TSSI) gRS: generic Reconciliation Sublayer
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OpenCores ZPU (embedded processor)
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ZPU Hello World CP2103 Memory 64 KB RS232 USB ZPU CORE Wishbone
Interconnect Open Cores UART 16550
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ZPU results Very small system
784 Flip-Flops (~ 6% LUT/CLB of XC6SLX45T) 64KB (= 27% RAMB16BWERs of XC6SLX45T) Open Cores => Several ZPU cores (but not the one we need): “ZPU_Core” Preffered type “ZPU_Core _small” uses Dual Port Memory “Zealot” = ZPU_Core + UART + Timer “ZY2000” = ZPU_Core + Whisbone (but using non IEEE VHDL libraries) => Took ZPU_Core and looked at ZY2000 to create ZPU_Core + Wishbone
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ZPU results-2 Tools operational:
Hardware Simulation (ModelSim scripts to fill Memory with “elf”) ISE, Memory Core Generator, BMM files, Data2Mem Software Cygwin, GNU toolchain Last Open Cores update = September 2009 But ZPU mailing list is alive and kicking Future study: Resetting the core sometimes creates a hang. Has got to do with software (over)writing the start-up vector at some point...
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Some more general remarks:
WR Specification! Link delay model John Eidson remarks How do we deal with delay asymmetry? Calibration? Thank you
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