1. Optohybrid V2 design status
Yifan Yang
05/11/2014

2. Agenda
Background
Status
Plan

3. Background

4. Background First prototype for full size GEB
Stepping stone for slice test
Initial the cooling system and mechanical design
Complete firmware design

5. Status Simple concept complex implementation
Not only one single system to be considered
Benefit from previous design

6. Top overview Power Clock Virtex6 VFAT control Configur-ation
Optical interface
Virtex6
Electrical interface
VFAT control

7. Top overview Power Clock Virtex6 VFAT control Configur-ation
Optical interface
Virtex6
Electrical interface
VFAT control

8. Power 15A~30A 3.3v,2.5v,1.8v,1.2v,1.0v,ripple ~10mv
Environment VS efficiency VS size VS cost
Radiation and magnetic field
Single LV or multi LV
DCDC or LDO
Power consumption highly depends on firmware design and related peripheral
Flexible for multiple possibility
Only LDO passed test, single LV
Able to accept external power supply for main power parts

9. Power MIC69502 Input 1.65v to 5.5v 0.5v dropout and 5A
Low efficiency but safe

10. Top overview Power Clock Virtex6 VFAT control Configur-ation
Optical interface
Virtex6
Electrical interface
VFAT control

11. Clock Frequency follow LHC clock Phase adjustable for front-end asic
Fixed latency for trigger path
Temporary solution before GBT is available
Buffer needed between cdce and FPGA

12. Top overview Power Clock Virtex6 VFAT control Configur-ation
Optical interface
Virtex6
Electrical interface
VFAT control

13. Configuration Radiation tolerance FLASH or NO FLASH
Configuration over HDMI cable
Configuration over optical fiber
Periodical reconfiguration

14. configuration
A:23
D:16
C:6
Multiboot support
Master/slave
45 IO

15. Top overview Power Clock Virtex6 VFAT control Configur-ation
Optical interface
Virtex6
Electrical interface
VFAT control

16. Optical interface QSFP or SFP Size VS cost
Mode, wavelength, bandwidth, power consumption, heating, stability
Test both QSFP and SFP and use belly-to-belly for cooling system test

17. Optical interface
20 GTX for belly to belly application

18. Top overview Power Clock Virtex6 VFAT control Configur-ation
Optical interface
Virtex6
Electrical interface
VFAT control

19. Electrical interface 4 pairs for JTAG (Buffer needed)
4 pairs for data or clock
4 single ended for test
UART for SEM
Program_b control
GBT/SCA test
VFAT3 emulator test
14pin header for small lemo mezzanine
2 pins for CCB LHC clock

20. Top overview Power Clock Virtex6 VFAT control Configur-ation
Optical interface
Virtex6
Electrical interface
VFAT control

21. VFAT2 control 9×2×24=432 Trigger and tracking data 6 I2C =12c Pull up
6 datavalid=12
3 T bus
3 MCLK lvds
3 RES
3 DAC to system monitor
480 IO
456 are differential pairs(95%)
OK for LVDS !
OK for SLVS ?

22. Top overview Power Clock Virtex6 VFAT control Configur-ation
Optical interface
Virtex6
Electrical interface
VFAT control

23. Virtex6 XC6VLX130T-1FF1156C 35mm×35mm 600 user IO 20 GTX up to 6.6Gbps
2.5v,1.0v,1.2v

24. Virtex 6 565(94.2%) VFAT2 control 480 IO Configuration 45 IO
Clock 20 IO
Test 20 IO
565(94.2%)
330 47
4.7
0.47
0.22
0.1
v1p0int 3 8
v2p5aux 2 1
v2p58_1
v2p58_0
v1p8
v2p5prom
V1P0MGT 16
v1p2mgt
Summary 5 19 37 32 17

25. Plan Schematic nearly finished (need review)
PCB estimated 12~14 layers
Pin assignment on FPGA need several Iteration
Expect finish design by the end of this year