1. HCAL DAQ Path Upgrades Current DCC Status New DCC Hardware Software
Selective Readout
ECAL overview
HCAL proposal
ZS threshold / data size study
Monte-Carlo work underway
E. Hazen

2. Current DCC Status No errors reported in HTR/DCC links
Few BcN and OrN problems
No LoS
DCCs running smoothly
DCC Spares are critical!
10 Spare boards exist
5 shipped to CERN where a net (-1) spares existed
After CASTOR, H2 etc there are only about 2 real spares
1 returned to Maryland for test stand (ongoing need)
2 have broken again after repair
2 in use in BU test stand
E. Hazen

3. New DCC
Two reviews held. Prototypes underway; production awaits decision from USCMS management
Hardware
PCB layout nearly done. Will send out after initial firmware done to avoid FPGA pinout problems.
Parts for 10 prototypes now on order FPGAs were donated by Xilinx.
We should have prototype boards (assembled) in early Nov.
Firmware
Well underway. Initially will use most VHDL from existing DCC main Xilinx chip (event builder).
Register footprint for Xilinx same as current DCC
”LRB” much simpler with no configuration registers
E. Hazen

4. New DCC Overview
Single VME slot; 15 HTR spigots, Ethernet, TTC, TTS on front
P3 rear transition module used for S-Link, selective readout
Xilinx
XC3S200A
FPGA
32MByte
DDR SDRAM
XC3SD1800A
64MByte
TTCrx
UMD
board
LVDS Tx
TTS
TTC
Buffers
VME
VME64x
S-Link
LSC
DAQ Data
TP Out
Readout bits in
Out In
6U transition module
at rear of crate
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5. Layout picture from Mr Wu
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6. Selective Readout
DAQ limits HCAL to 2k bytes / FED (1 DCC, 288 channels)
60 words per half-HTR (24 channels) per event average (1 word = 1 TP or 1 Digi)
This is 15% occupancy maximum (for 10 time samples)
We must set a corresponding zero-suppression threshold in each HTR so that we meet this limit
We may miss important physics because of this
Selective readout would make better use of this bandwidth
New DCC will be capable of buffering non-ZS data from
E. Hazen

7. ZS Event Sizes Now Global run 62064 first 1k Evt (from EricDIM)
All HCAL
mean = 3600 bytes
HBHEa
mean = 4600 bytes
(HBHEb/c
are very similar) HO
mean = 2200 bytes HF
mean = 2400 bytes
E. Hazen

8. Selective Readout Proposal
Send all HCAL TP and ECAL SR flags to (new) processor
Apply readout selection algorithms
Send readout flags back to (new) DCC to control readout
Let's briefly review the ECAL system, which is already installed...
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9.
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10.
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11.
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12. ECAL Selective Readout Processor
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13. spare opto transmitters)
We can get a copy of
the SR flags from
here (SRP)
or here (DCC)
(both have sufficient
spare opto transmitters)
E. Hazen

14. HCAL Selective Readout
ECAL
TCCs
TT Flags
ECAL SRP
ECAL
DCCs
SR Flags
Fibers
(54)
SLink
HCAL
Readout
Processor
SR flag
copy to HCAL
HCAL
DCCs
HCAL TPs
each L1A
~ 30MBytes/sec
Fibers
or cables
(32/64)
Readout mask
288 bits = 4 MBytes/s
SLink
DAQ Data
Channels selected by
readout mask only
E. Hazen

15. Hardware Required SR Processor for HCAL would need:
= 86 optical inputs (or 32 from HCAL could be Cat5)
32 optical or Cat5 outputs
Intercommuncation between modules
Relatively modest processing FPGA resources
Two options come to mind:
ECAL SRP boards (spares available for tests; could build more)
+ standard 6U VME, already designed
– relatively expensive
uTCA Matrix boards
+ get early experience with uTCA
– boards not available yet
– new technology
E. Hazen

16. Monte Carlo work
Initially, need occupancy vs threshold (with correct pedestals and noise)
We will want this anyway to set thresholds for 100kHz triggers
Work starting (Jim, Arno)
Analysis of various SR algorithms
Readout HCAL behind electrons, photons from ECAL
Readout HO behind HB
Lower threshold around jets in HCAL
E. Hazen

17. Backup Slides
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18. Selective Readout
EVO meeting with J.C. DaSilva, I. Mandjavidze, P. Gras of ECAL group on 9/11. Learned several things:
ECAL Selective readout flags can be duplicated in ECAL SRP and sent to us on spare fiber outputs. ECAL guys did a trial fit in their firmware and confirmed this is no problem.
Existing ECAL SRP hardware is actually a good fit for our needs. We would need 8 of their boards for an HCAL system. They have 6 spares; presumably we could borrow 1 or 2 for a test.
I asked ECAL for a cost estimate. They say:
Total 5320€ per card (!) Maybe we could build them cheaper
1) VME board with soldered components: 2500€
including 1900€ xc2vp70-6-f1704 Virtex2Pro FPGA from Xilinx
2) Four pluggable parallel optic modules 1500€
3) Production 1250€ (PCB + component soldering)
including systematic X-ray, Takaya flying probe and JTAG tests
The alternative to use the maxtrix uTCA board is viable too, but the ECAL hardware is available now
E. Hazen

19. HTR Readout Limitations
Selective Readout requires that HTR send non-zero-suppressed data. For 10 timesamples + 1 TP per channel each HTR must send * (24 ch) + (20 words overhead) = 284 words at 100kHz this is 28MHz word rate The HTR/DCC link runs at 40MHz, so this should in principle be ok BUT, a series of simple tests show that the current limit is about 9 MHz word rate before HTR starts to send empty events.
Tullio says this is no surprise... it was not optimized, however the current design is limited to 20MHz at best (too slow). This can probably be fixed in the HTR firmware
E. Hazen