1. PowerPC SCC port and EC/ECP HDLC controller Communication
SBO, Q2/2005 by James Lee

2. Overview
HDLC is the abbreviation for High-Level Data Link Control published by the International Standards Organization (ISO).
The HDLC protocol is defined in ISO3309 and related ISO standards. HDLC was the result of an effort by the international community to develop a standard for data link communication.
This data link protocol such as LAPB, LAPD, LLC and SDLC are all based on the HDLC protocol with a few modification.
Lattice EC/ECP supports the HDLC core for CCITT, CRC16 and CRC32 standard, also supports Embedded block ram for Data queuing.

3. Index Feature of HDLC controller Block diagram of HDLC controller
Application of HDLC controller
Tx data modification for accommodation with SCC
Modification Source code
Samsung Design description

4. Features of HDLC controller
• Parameterizable number of HDLC channels in multi-channel design. Each channel corresponds to
a DS0 channel in the TDM & PCM highway.
• CRC (Cyclic Redundancy Check) check with parameterizable FCS (Frame Check Sequence)
length and arbitrary polynomials.
• Flag insertion and detection
• Abort generation and detection
• Zero insertion and deletion
• Idle insertion
• Flag sharing between HDLC frames
• Recognize as two continuous flags
• Conforms to ISO/IEC 3309

5. ( HDLC Tx/Rx controller for CCITT, CRC16, CRC32)
Block Diagram of HDLC controller
EC/ECP
Rx HDLC Controller
Packet Size
FIFO
CPU
Interface
Block Rx
Control
Logic
CPU
Line
Card
R_Buffer 7
F_Detect
Z_Unstuff
BIT_CNT
CRC_CHK
R_Control
R_Shift
A_Detect
STATUS
Rx_Data Rx
HDLC
256x8
Rx FIFO
Rx Data
Data
Rx_Clk
8bits
512x8
Add
Interrupt
Control
( HDLC Tx/Rx controller for CCITT, CRC16, CRC32)
CPU_CS
Tx HDLC Controller
Register
Block
CPU_WRn
CPU_DSn
F_INSERT
T_Buffer 7
T_Shift
CRC_GEN
Z_Stuff
A_Insert
T_Control
Tx_Clk
Tx FIFO
CPU_Clk
Tx Data
CPU_INTn
8bits
512x8 Tx
HDLC Tx
Control
Logic Tx
Modification
Logic
Tx_Data

6. Application of HDLC controller
Line Card
Processor Card
PowerPC
SCC
Line Card
PowerPC
SCC
EC/ECP/XP
HDLC
Controller .
PowerPC .
Line Card
PowerPC
SCC
Line Card
PowerPC
SCC
SCC (Serial Communications Controllers)
HDLC (High-level Data Link Control)

7. HDLC Frame Format

8. Tx Modification for accommodating HDLC format with SCC1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F 7 E 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 F 7 E 7 E 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9 F 7 E 7 E 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C F 7 E 7 E
FCS
Flag
When the last FCS byte is hx1F, hx9F, hx3F, hxEF, Tx data modulation is needed to avoid abort
alarm in PowerPC SCC port

9. Abort Alarm is occurred in SCC port
Tx Modification for accommodation with SCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F 7 E
Abort Alarm is occurred in SCC port
FCS
Flag
Flag
Whenever there are five consecutive 1’s followed by a zero, the zero will be ignored in PowerPC
SCC port. So the zero which is located between FCS and Flag is ignored and SCC port
recognized Abort status 1
FCS
Modified Flag F 3 7 E
Flag
To avoid Abort status, Modified flag is need

10. Modification source code
Process(RST, CLK, Int0_reg)
begin
if rst = '0' then
Int0_reg <= ( others => '0');
elsif CLK'event and CLK = '0' then
if (Int0_reg(14 downto 0) = " ") then
Int0_reg(16 downto 0) <= int0_reg(15) & " " & txdata0a;
else
Int0_reg(16 downto 0) <= Int0_reg(15 downto 0) & txdata0a;
end if;
end process;
Txdata0 <= Int0_reg(16);