1. Contents Electronics (Logic Gates) Logic Gates 1 NOT gate 2 OR gate
3 AND gate
4 NOR gate
5 NAND gate
6 NOR-Universal Logic Gate
7 NAND-Universal Logic Gate
Logic Gates

2. NOT gate NOT Logic Gates (Inverter gate)
A NOT gate is a one-input-one-output logic gate A Q
Logic Gates
A = input, Q = output

3. NOT
NOT gate
(Inverter gate)
Q = ?
Logic Gates
When A = 0

4. NOT
NOT gate
(Inverter gate) 1
Logic Gates
When A = 0, Output Q = 1

5. NOT Logic Gates NOT gate (Inverter gate) 11
Logic Gates
When A = 0, Output Q is NOT 0, Hence = 1

6. NOT
NOT gate
(Inverter gate) 1 Q
Logic Gates
When A = 1

7. NOT
NOT gate
(Inverter gate) 1
Logic Gates
When A = 1, Output Q = 0

8. NOT Logic Gates NOT gate (Inverter gate) 1
Logic Gates
When A = 1, Output Q is NOT 1, Hence = 0

9. NOT Logic Gates NOT gate (Inverter gate) A Q 1 Truth Table 1 11 1 1
Logic Gates
When A = 0, Output Q is NOT 0, Hence = 1
When A = 1, Output Q is NOT 1, Hence = 0

10. OR
OR gate
The simplest OR gate is a two-input-one-output logic gate A Q B
Logic Gates
A & B = inputs, Q = output

11. OR
OR gate
Q = ?
Logic Gates
When A = 0, B = 0

12. OR
OR gate
Q = 0
Logic Gates
When A = 0, B = 0, 0 OR 0 = 0

13. OR
OR gate
Q = 1 1
Logic Gates
When A = 0, B = 1, 0 OR 1 = 1

14. OR
OR gate 1
Q = 1
Logic Gates
When A = 1, B = 0, 1 OR 0 = 1

15. OR
OR gate 1
Q = 1 1
Logic Gates
When A = 1, B = 1, 1 OR 1 = 1

16. OR gate OR Logic Gates A B Q 1 Truth Table Q = 0 Q = 1 1 1 Q = 1 1
Q = 0 A B Q 1
Q = 1 1 1
Q = 1 1
Logic Gates
Q = 1 1
OR gate = Output is 1 when at least one input is 1

17. AND gate AND Logic Gates
The simplest AND gate is a two-input-one-output logic gate
Q = ?
Logic Gates
A & B = inputs, Q = output

18. AND
AND gate
Q = 0
Logic Gates
When A = 0, B = 0, 0 AND 0 = 0

19. AND
AND gate
Q = 0 1
Logic Gates
When A = 0, B = 1, 0 AND 1 = 0

20. AND
AND gate 1
Q = 0
Logic Gates
When A = 1, B = 0, 1 AND 0 = 0

21. AND
AND gate 1
Q = 1 1
Logic Gates
When A = 1, B = 1, 1 AND 1 = 1

22. AND gate AND Logic Gates A B Q 1 Truth Table Q = 0 Q = 0 1 1 Q = 0 1
Q = 0 A B Q 1
Q = 0 1 1
Q = 0 1
Logic Gates
Q = 1 1
AND gate = Output is 1 only when all inputs are 1

23. NOR gate (NOT-OR = NOR, opposite of OR)
The simplest NOR gate is a two-input-one-output logic gate A Q B
Logic Gates
A & B = inputs, Q = output

24. NOR
NOR gate
Q = 1
Logic Gates
When A = 0, B = 0, 0 NOR 0 = 1

25. NOR
NOR gate
Q = 0 1
Logic Gates
When A = 0, B = 1, 0 NOR 1 = 0

26. NOR
NOR gate 1
Q = 0
Logic Gates
When A = 1, B = 0, 1 NOR 0 = 0

27. NOR
NOR gate 1
Q = 0 1
Logic Gates
When A = 1, B = 1, 1 NOR 1 = 0

28. NOR gate NOR Logic Gates A B Q 1 Truth Table Q = 1 Q = 0 1 1 Q = 0 1
Q = 1 A B Q 1
Q = 0 1 1
Q = 0
Logic Gates 1
Q = 0 1
NOR gate = Output is 1 only when all inputs are 0

29. NAND gate (NOT-AND = NAND, opposite of AND)
The simplest NAND gate is a two-input-one-output logic gate A
Q = ? B
Logic Gates
A & B = inputs, Q = output

30. NAND
NAND gate
Q = 1
Logic Gates
When A = 0, B = 0, 0 NAND 0 = 1

31. NAND
NAND gate
Q = 1 1
Logic Gates
When A = 0, B = 1, 0 NAND 1 = 1

32. NAND
NAND gate 1
Q = 1
Logic Gates
When A = 1, B = 0, 1 NAND 0 = 1

33. NAND
NAND gate 1
Q = 0 1
Logic Gates
When A = 1, B = 1, 1 NAND 1 = 0

34. NAND gate NAND Logic Gates A B Q 1 Truth Table Q = 1 Q = 1 1 1 Q = 1 1
Q = 1 A B Q 1
Q = 1 1 1
Q = 1 1
Q = 0
Logic Gates 1
NAND gate = Output is 0 when all inputs are 1

35. Link inputs B & C together (to a same source).
Universal Gates
How to use NOR gate to build a NOT gate?
Truth Table A B C Q 1 A Q B C
Hint!
Link inputs B & C together (to a same source).
Logic Gates
When A = 0, B = C = A = 0
When A = 1, B = C = A = 1

36. Universal Gates Logic Gates How to use NOR gates to build an OR gate?
Truth Table A B C D E Q 1
NOR
NOT A D C Q B E
Hint 1 : Use 2 NOR gates
Logic Gates
Hint 2 : From a NOR gate, build a NOT gate
Hint 3 : Put this “NOT” gate after a NOR gate

37. Hint 2 : From 2 NOR gates, build 2 NOT gates
Universal Gates
How to use NOR gates to build an AND gate?
Truth Table A B C D Q 1 A B C D Q
Hint 1 : Use 3 NOR gates
Logic Gates
Hint 2 : From 2 NOR gates, build 2 NOT gates
Hint 3 : Each “NOT” gate is an input to the 3rd NOR gate

38. Universal Gates Logic Gates How to use NOR gates to build a NAND gate?Q E
Truth Table A B C D E Q 1
Hint 1 : Use 4 NOR gates
Hint 2 : Use 3 NOR gates to build a NAND gate
Hint 3 : Use the 4th NOR gate to build a NOT gate
Logic Gates
Hint 4 : Insert “NOT” gate after “NAND” gate
Hint 5 : NOT-NAND = AND

39. Link inputs B & C together (to a same source).
Universal Gates
How to use NAND gates to build a NOT gate?
Truth Table A Q C B A B C Q 1
Hint!
Link inputs B & C together (to a same source).
Logic Gates
When A = 0, B = C = A = 0
When A = 1, B = C = A = 1

40. Universal Gates Logic Gates
How to use NAND gates to build an AND gate?
Truth Table A B C Q 1
NAND
NOT A C Q B
Hint 1 : Use 2 NAND gates
Logic Gates
Hint 2 : From a NAND gate, build a NOT gate
Hint 3 : Put this “NOT” gate after a NAND gate
Hint 4 : NOT-NAND = AND

41. Hint 2 : Use 2 NAND gates to build 2 NOT gates
Universal Gates
How to use NAND gates to build an OR gate?
Truth Table A B C D Q A B C D Q 1
Hint 1 : Use 3 NAND gates
Logic Gates
Hint 2 : Use 2 NAND gates to build 2 NOT gates
Hint 3 : Put the 3rd NAND gate after the 2 “NOT” gates

42. Hint 2 : Use 3 NAND gates to build an OR gate
Universal Gates
How to use NAND gates to build a NOR gate?
Truth Table A B C D Q E A B C D E Q 1
Hint 1 : Use 4 NAND gates
Logic Gates
Hint 2 : Use 3 NAND gates to build an OR gate
Hint 3 : Use a NOR gate to build a NOT gate
Hint 4 : Put the “NOT” gate after “OR” gate

43. Integrated Circuits
The first integrated circuits were manufactured independently by two scientists:
Jack Kilby of Texas Instruments filed a patent for a "Solid Circuit" made of germanium on February 6, 1959.
Robert Noyce of Fairchild Semiconductor was awarded a patent for a more complex "unitary circuit" made of Silicon on April 25, 1961.
Noyce credited Kurt Lehovec of Sprague Electric for the principle of p-n junction isolation caused by the action of a biased p-n junction (the diode) as a key concept behind the IC.[3]

44. Integrated Circuits
"Small-Scale Integration" (SSI) - used circuits containing transistors numbering in the tens.
Devices which contained hundreds of transistors on each chip, were called "Medium-Scale Integration" (MSI).
"Large-Scale Integration" (LSI) in the mid 1970s, came with tens of thousands of transistors per chip.
"Very Large-Scale Integration" (VLSI). This could be said to start with hundreds of thousands of transistors in the early 1980s, and continues beyond several billion transistors as of 2007.
ULSI that stands for "Ultra-Large Scale Integration" was proposed for chips of complexity of more than 1 million transistors

45. Notable ICs
The 555 common multivibrator subcircuit (common in electronic timing circuits)
The 741 operational amplifier
7400 series TTL logic building blocks
4000 series, the CMOS counterpart to the 7400 series
Intel 4004, the world's first microprocessor
The MOS Technology 6502 and Zilog Z80 microprocessors, used in many home computers

46. IC manufacturers
Agere Systems (formerly part of Lucent, which was formerly part of AT&T)
Agilent Technologies (formerly part of Hewlett-Packard, spun-off in 1999)
Alcatel
Altera
AMD (Advanced Micro Devices; founded by ex-Fairchild employees)
Analog Devices
ATI Technologies (Array Technologies Incorporated; acquired parts of Tseng Labs in 1997; in 2006, became a wholly-owned subsidiary of AMD)
Atmel (co-founded by ex-Intel employee)
Commodore Semiconductor Group (formerly MOS Technology)
Fairchild Semiconductor (founded by ex-Shockley Semiconductor employees: the "Traitorous Eight")

47. IC Advantages Small size and weight Improved performance Low cost
High reliability
Low power consumption
Increased operating speed
Less vulnerability to parameter variation
Easy troubleshooting
Simple design of systems
Standard packaging

48. Limitations of IC
Unable to dissipate large amount of power due to small size
Inductors and transformers cannot be produced in IC form

49. Why Silicon?
1) Silicon devices can operate up to 150OC versus 100OC for germanium. Silicon grows a stable oxide (SiO2), which is one of the very important process steps in the fabrication of ICs. In fact, planar processing technology derives its success from the properties of thermally grown SiO2. Germanium oxide is unsuited for device applications.
2) The intrinsic, i.e. undoped, resistivity of germanium is about 47Ω–cm, which precludes the fabrication of rectifying devices with high breakdown voltages.
In contrast, the intrinsic resistivity of silicon is about 23 x 104 Ω–cm. Thus High - voltage rectifying devices are practical with silicon.
3) Over the years silicon technology is very highly developed. Also electronic grade germanium is now more costly than silicon.

50. IC Classification Based on Uses and Applications
Linear ICs - Operational amplifiers, Voltage regulators,voltage comparators, Oscillators, modulators, timer
Signals are represented by analog variables
Digital ICs – Logic gates, filp-flops, counters, memory chips, microprocessors
Signals are represented by binary number system

51. Classification of ICs Based on fabrication Monolithic ICs
Thick and thin film ICs
Hybrid or multichip ICs.

52. Monolithic ICs The word mono means single and litho means stone.
Thus monolithic circuit is built into a single stone or single crystal.
In this, the active components (diodes, transistors, etc) and passive components (resistors, capacitors) are all formed in the silicon slice by diffusing impurities into the selected regions to modify the electrical characteristics and where necessary to form PN junctions. The diffusion operations are carried out on the top surface of the silicon slice and also the element contact regions are formed on the same surface, so that they can be interconnected to form the complete electronic circuit. All the components are automatically part of the same chip.

53. Thick and thin film ICs
The essential difference between thick film and thin film is not their relative thickness but the method of depositing the film.
These ICs are not formed within a Si wafer but on the surface of an insulating substrate such as glass or ceramic material.
Moreover only passive components (resistors, capacitors) are formed through thick or thin film techniques on the insulating surface.
The active elements (transistors, diodes) are added externally as discrete elements to complete a functional circuit. These discrete active components are frequently produced by using monolithic process.

54. Hybrid or Multi-chip ICs
As the name implies, such circuits are formed by interconnecting a number of individual chips or by a combination of film and monolithic IC techniques.
In such ICs, active components are formed within a Si wafer, using monolithic technique which is subsequently with an insulating layer such as SiO2.
Film techniques are then employed to form passive components on the SiO2 surface.
Connections are made from the film to the monolithic structure through “Windows” cut in the SiO2 layer.

55. Monolithic Integrated Circuits
Circuits that are placed entirely on a single chip of semiconductor (usually Si) are called monolithic integrated circuits.
Advantages - mass production by batch processing is possible.
Many identical circuits are fabricated simultaneously on a Si wafer (up to 12”diameter), which is then sawed into many chips.
Each chip is finally enclosed in plastic or ceramic packages to become an IC.

56. Monolithic IC Fabrication - EPITAXIAL METHOD.
The EPITAXIAL process involves depositing a very thin layer of silicon to form a uniformly doped crystalline region (epitaxial layer) on the substrate.
Components are produced by diffusing appropriate materials into the epitaxial layer

57. EPITAXIAL METHOD.
Planar-epitaxial transistor

58. The steps in the fabrication process
Planar-diffused transistor

59. Wafers in a diffusion oven

60. The steps in the fabrication process
1. An oxide coating is thermally grown over the n-type silicon starting material.

61. The steps in the fabrication process
2.    By means of the photolithographic process, a window is opened
through the oxide layer. This is done through the use of masks

62. Photolithography
In photolithography, the pattern is created photographically on a substrate (silicon wafer)
Photolithography is a binary pattern transfer: there is no gray-scale, color, nor depth to the image
This pattern can be used as a resist to substrate etchant, or a mold, and other forms of design processes
The steps involved are wafer cleaning, photoresist application, soft baking, mask alignment, and exposure and development

63. Photolithography process

64. Spin on the photo resist to the surface of the wafer
Deposit a layer of SiO2 (silicon dioxide) on the surface of the wafer to serve as a barrier.
Spin on the photo resist to the surface of the wafer
Standard methods are to use high spin coaters
RPM:
Time:
Produces a thin uniform layer of photoresist on the wafer surface.

65. Photoresist
Photoresist is an organic polymer which changes its chemical structure when exposed to ultraviolet light.
It contains a light-sensitive substance whose properties allow image transfer onto a printed circuit board.
There are two types of photoresist: positive and negative

66. Diagram:
Exposure to UV light causes the resist to polymerize, and thus be more difficult to dissolve
Developer removes the unexposed resist
This is like a photographic negative of the pattern
Exposure to UV light makes it more soluble in the developer
Exposed resist is washed away by developer so that the unexposed substrate remains
Results in an exact copy of the original design

67. Mask Alignment and Exposure
Photomask is a square glass plate with a patterned emulsion of metal film on one side
After alignment, the photoresist is exposed to UV light
Three primary exposure methods: contact, proximity, and projection

68. Exposure Methods

69. Photoresist Developer
Highly-pure buffered alkaline solution
Removes proper layer of photo resist upon contact or immersion
Degree of exposure affects the resolution curves of the resist

70. The steps in the fabrication process
 3.The base of the transistor is formed by placing the wafer in a diffusion furnace containing a p- type impurity, such as boron. By controlling  the temperature of the oven and the length of time that the wafer is in the oven, you can control the amount of boron diffused through the window (the boron will actually spread slightly beyond the window opening). A new oxide layer is then allowed to form over the area exposed by the window.

71. The steps in the fabrication process
4.  A new window, using a different mask much smaller than the first, is opened through the new oxide layer.

72. The steps in the fabrication process
5. An n-type impurity, such as phosphorous, is diffused through the new window to form the emitter portion of the transistor. Again, the diffused material will spread slightly beyond the window opening. Still another oxide layer is then allowed to form over the window.

73. The steps in the fabrication process
6.  By means of precision-masking techniques, very small windows (about inch in diameter) are opened in both the base and emitter regions of the transistor to provide access for electrical currents.

74. The steps in the fabrication process
7.  Aluminum is then deposited in these windows and alloyed to form the leads of the transistor or the IC. (Note that the pn junctions are covered throughout the fabrication process by an oxide layer that prevents contamination.)