1. Chapter 5 Combinational Logic 组合逻辑

2. Combinational
Logic circuit
Logic circuit
Sequential
Logic circuit

3. 5.1 Basic Combinational Circuits
AND-OR
AND-OR-Invert
XOR
XNOR
NAND
NOR

4. 1 AND-OR Logic
X=AB+CD
An AND-OR circuit directly implements SOP expression, assuming the complements of the variables are available. D A B C X
& 1 A B C D X
ANSI standard distinctive shape symbols
ANSI standard rectangular outline symbols

5. Example chip: 74HC58 VCC GND 74HC58 (CMOS): dual AND-OR2 3 4 6
& 1 9 11 8 10 12 1 13
VCC 7 14
74HC58 (CMOS): dual AND-OR
1 two inputs AND-OR.
1 three inputs AND-OR

6. 2 AND-OR-Invert Logic
An AND-OR-Invert can be used to implement POS expression. D A B C X
& 1 A B C D X

7. Example chip: 74LS51 VCC GND 74LS51 : dual 2-wide AND-OR-Invert3 4 6
& 1 9 11 8 10 12 1 13
VCC 7 14
74LS51 : dual 2-wide AND-OR-Invert
1 two inputs AND-OR-Invert.
1 three inputs AND-OR-Invert

8. 3 Exclusive-OR (XOR)异或 A B C A B C

10. 4 Exclusive-NOR (XNOR)同或A B C A B C

12. 5-2 IMPLEMENTING COMBINATIONAL LOGIC 实现组合逻辑

13. From a Boolean Expression to a Logic Circuit
Example:

14. From a Boolean Expression to a Logic Circuit
Example:

15. From a Truth Table to a Logic Circuit
Example:

16. 5-3 THE UNIVERSAL PROPERTY OF NAND AND NOR GATES 与非门和或非门的通用特征

17. The NAND Gate as a Universal Logic Element
The NAND gate can be used to produce the NOT, AND, OR, and NOR operations.

18. The NOR Gate as a Universal Logic Element
The NOR gate can be used to produce the NOT, AND, OR, and NAND operations.

19. 5-4 COMBINATIONAL LOGIC USING NAND AND NOR GATES 使用与非门和或非门的组合逻辑

20. 5 Combinational Logic Using NAND and NOR Gates
Negative-OR
Negative-AND

21. Example: Implementing the following expression using NAND gates:
Solution: A B C D X

22. Example: Implementing the following expression using NOR gates:
Solution: A B C D X

23. NAND Logic

24. NOR Logic

25. 5-5 Logic Hazards Objective: Combinational logic hazards Reasons
Checking
Eliminating methods

26. Combinational Logic Hazards
Static hazard
Dynamic hazard

27. Static hazards 1 1 glitches 1 Static hazards have two cases:
Static 1 : an output variable should be a 1, but goes to 0 momentarily as a result of an input variable changing.
Static 0 : an output variable should be a 0, but goes to 1 momentarily as a result of an input variable changing. 1 1
glitches 1

28. Static 1 hazards example

29. glitch

30. Static-0 hazards example

32. Checking static hazards:
If the circuit can be simplified as follows A+A=1 or AA=0, it has the potential to cause static hazards.

33. Static-0
Static-1

34. Exercise

35. exercise

36. 5-6 OPERATION WITH PULSE WAVEFORMS 具有脉冲波形的逻辑电路运算

37. Logical Operation is the Same
The logical operation of a gate is the same for pulse inputs as for constant-level inputs.

38. Homework
Problems: 2 6d 9d 10c 12 22e 24g 27