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Runtime-Quality Tradeoff in Partitioning Based Multithreaded Packing

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Presentation on theme: "Runtime-Quality Tradeoff in Partitioning Based Multithreaded Packing"— Presentation transcript:

1 Runtime-Quality Tradeoff in Partitioning Based Multithreaded Packing
FACULTY OF ENGINEERING AND ARCHITECTURE Runtime-Quality Tradeoff in Partitioning Based Multithreaded Packing Dries Vercruyce Elias Vansteenkiste and Dirk Stroobandt Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

2 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Toolflow HDL description Synthesis Technology mapping Placement Routing Packing Packing FPGA configuration Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

3 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Packing Seed based Partitioning based Bottom-up approach Seed block Affinity metric Top-down approach Hierarchical partitioning of the circuit Fast Tight packing Slow Constraints Local minima No multithreading Quality of results Multithreading Once a circuit is split in half, we thread both subcircuits independently during partitioning. This leads to the opportunity of multithreading. QoR Wirelength and channelwidth Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

4 Constraints Fixed # LUT/FF Fixed # input pins Complete/sparse crossbar
Local interconnect LUT FF BLE Fixed # LUT/FF Fixed # input pins Complete/sparse crossbar

5 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Related work Constraints enforcing step required Simplified architectures Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

6 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Contributions Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

7 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Contributions No constraints enforcing step required Fast multithreaded packing Multithreaded seed based packing (MultiPart) Realistic heterogeneous architectures (MultiPart) Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

8 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Outline Packing Contributions Circuit partitioning PartSA MultiPart Experiments Conclusions and Future work Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

9 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Circuit partitioning A FF FF MULT B FF FF LUT LUT FF FF Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

10 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Circuit partitioning A B Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

11 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
PartSA N 1 1 1 1 1 1 1 1 1 Clustering based on design hierarchy Simulated annealing fine-tuning cost function Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

12 Simulated annealing: cost function
Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

13 Simulated annealing: cost function
PTH PMAX Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

14 Problem: cutting critical paths
Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

15 Problem: cutting critical paths
Wedge

16 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Problems with PartSA Partitioning runtime increases as you go deeper in the hierarchy Unused threads on first hierarchy levels Large amount of subcircuits Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

17 Problems with PartSA Partitioning runtime increases as you go deeper in the hierarchy Hard to target commercial architectures Commercial architectures contain sparse local interconnect crossbars Legal solution after block swap? Detailed routing required in kernel of simulated annealing Infeasible due to the large amount of required swaps Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

18 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
MultiPart No partitioning required on deep hierarchical levels Detailed routing is feasible with seed based packing Subcircuits are threaded independently Multithreaded seed based packing Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

19 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Partition depth Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

20 Problem: cutting critical paths
SDC File Even though timing edges are added during partitioning, there is a chance that a critical path is cut during partitioning. Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

21 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Experimental results None of the packers shown before is able to pack the VTR benchmarks and is not publicly available. All results are related to AAPack Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

22 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Total wirelength Related to AAPack! Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

23 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Minimum channel width Smaller and cheaper FPGA’s Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

24 Execution time and scaling behaviour
Name Area Runtime speed-up PartSA MultiPart LU8PEEng 770K 1.7x 2.6x LU32PEEng 2.7M 2x 3.3x LU64PEEng 5.3M 2.3x 4x

25 Summary Total wirelength Critical path delay Runtime speed-up
K6_N10_40nm (complete crossbar) PartSA -26% -1.5% 1.8x MultiPart -12% -2.6% 2.7x K6_N10_gate_boost_0.2V_22nm (sparse crossbar) -20% -3.7% 2.9x Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

26 Conclusion and future work
Partitioning based packing methods Design hierarchy preserved Multithreaded parallelism Higher quality packing in less runtime Total wirelength Minimum channel width Critical path delay Future work: Extend MultiPart Titan benchmark design suite Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

27 Extra: Results for Titan
Total wirelength Critical path delay Runtime speed-up VTR -20% -3.7% 2.9x Titan -28% -6% 3.6x Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

28 Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016
Acknowledgement Supported by European Commission H2020-FETHPC EXTRA project: The author is supported by a PhD grant of the Research Foundation Flanders (FWO) Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

29 Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012
ADDITIONAL SLIDES Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

30 Multithreaded partitioning
CPU with 4 cores Ghent University – Computer Systems Lab – FPL 2016 – 30 August 2016

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