1. Digital Integrated Circuits A Design Perspective
EE141
Digital Integrated Circuits A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Introduction

2. EDA Tools
Layout Design Tool
SPICE
VHDL (synthesis and simulation)

3. Layout Editor (Ledit from Tanner EDA tools)
Mentor Graphics/Cadence
SPICE (ORCAD which is used in Cadence design tools)
VHDL ( Xilinx ISE webpack and ModelSim, used in cadence, mentor and Synopsis EDA tools)

4. Reference books
Digital Integrated Circuits, by:- Jan.M.Rabaey, Anantha Chandrakasan and Borivoje Nikolic
Principles of CMOS VLSI Design, by:- Niel Weste, Kamran Ishraghian
CMOS VLSI Design, by:- Weste-Harris
PSPICE using ORCAD, by:- M.H. Rashid
VHDL Primer, by:- J. Bhaskar
Plenty of material from INTERNET

5. What is this book all about?
Introduction to digital integrated circuits.
CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies.
What will you learn?
Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability

6. Digital Integrated Circuits
Introduction: Issues in digital design
The CMOS inverter
Combinational logic structures
Sequential logic gates
Design methodologies
Interconnect: R, L and C
Timing
Arithmetic building blocks
Memories and array structures

7. Introduction
Why is designing digital ICs different today than it was before?
Will it change in future?

8. The First Computer - use the decimal number system rather
than the binary representation
“store” and “mill” (execute), 2 cycle opn.
used pipelining to speed up the
execution of the addition operation
complexity and the cost problem
Working part of Babbage’s Difference Engine I (1832), the first known
automatic calculator (from [Swade93], courtesy of the Science Museum of London).

9. Digital Electronics- Era
Early digital electronics systems were based on magnetically controlled switches (or relays). They were mainly used in the implementation of very simple logic networks. Examples of such are train safety systems, where they are still being used at present.
The age of digital electronic computing only started in full with the introduction of the vacuum tube. While originally used almost exclusively for analog processing, it was realized early on that the vacuum tube was useful for digital computations as well.

10. ENIAC - The first electronic computer (1946)
- vacuum tube based
computer
- UNIVAC I (the first
successful commercial
computer)
Integration Density:
80 feet long, 8.5 feet high
and several feet wide and
incorporated 18,000
vacuum tubes.
- Reliability problems and excessive power consumption made the implementation of larger
engines economically and practically infeasible.

11. The Transistor Revolution
invention of the transistor
at Bell Telephone
Laboratories in [ Bardeen], followed by the introduction of the bipolar transistor by Schockley in
1949 [Schockley]
First transistor
Bell Labs, 1948

12. The First Integrated Circuits
Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966
- TTL had the advantage, however, of offering a
higher integration density and was the basis of the first integrated circuit revolution.
In fact, the manufacturing of TTL components is what spear-headed the first large semiconductor companies such as Fair-child, National, and Texas Instruments.
- The family was so successful that it composed the largest fraction of the digital semiconductor market until the 1980s.

13. Ultimately, bipolar digital logic lost the battle for hegemony in the digital design world for exactly the reasons that haunted the vacuum tube approach.
The large power consumption per gate puts an upper limit on the number of gates that can be reliably integrated on a single die, package, housing, or box.
Although attempts were made to develop high integration density, low-power bipolar families (such as I2L—Integrated Injection Logic [Hart72]).
The torch was gradually passed to the MOS digital integrated circuit approach.

14. MOS Device issues
The basic principle behind the MOSFET transistor (originally called IGFET) was proposed in a patent by J. Lilienfeld (Canada) as early as 1925, and, independently, by O. Heil in England in 1935.
Insufficient knowledge of the materials and gate stability problems, however, delayed the practical usability of the device for a long time. Once these were solved, MOS digital integrated circuits started to take off in full in the early 1970s.
The complexity of the manufacturing process delayed the full exploitation of these devices for two more decades.
The first practical MOS integrated circuits were implemented in PMOS-only logic and were used in applications such as calculators. The second age of the digital integrated circuit revolution was inaugurated with the introduction of the first microprocessors by Intel in 1972 (the 4004) and 1974 (the 8080).

15. Intel 4004 Micro-Processor
First 4Kbit MOS memory :1970
1971
1000 transistors
1 MHz operation
Handcrafted
These processors were implemented in NMOS-only logic, which has the advantage of higher speed over the PMOS logic.

16. These events were at the start of a truly astounding evolution towards ever higher integration densities and speed performances, a revolution that is still in full swing right now.
In the late 1970s, NMOS-only logic started to suffer from the same plague that made high-density bipolar logic unattractive or infeasible: power consumption.
This requirement, combined with progress in manufacturing technology, finally tilted the balance towards the CMOS technology, and this is where we still are today.

17. Intel Pentium (IV) microprocessor
year 2000
~40 million transistors
Hierarchical approach

18. Interestingly enough, power consumption concerns are rapidly becoming dominant in CMOS design as well, and this time there does not seem to be a new technology around the corner to alleviate the problem.
Although the large majority of current ICs are implemented in the MOS technology, other technologies come into play when very high performance is at stake.
An example of this is the BiCMOS : bipolar and MOS devices on the same die. BiCMOS is used in high-speed memories and gate arrays.

19. When even higher performance is necessary, other technologies emerge besides the bipolar silicon ECL family—Gallium-Arsenide, Silicon-Germanium and even superconducting technologies.
These technologies only play a very small role in the over-
all digital integrated circuit design scene. With the ever increasing performance of CMOS, this role is bound to be further reduced with time.

20. Moore’s Law (amazing visionary)
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will double its effectiveness every 18 months
* Integration density and performance of integrated circuits have gone through an astounding revolution in the last couple of decades.

21. Moore’s Law
Electronics, April 19, 1965.

22. Evolution in Memory Complexity
As can be observed, integration complexity doubles approximately every 1 to 2 years. As a result, memory density has increased by more than a thousandfold since 1970.

23. Transistor Counts 1 Billion Transistors K 1,000,000 100,000 10,000
Pentium® III
10,000
Pentium® II
Pentium® Pro
1,000
Pentium®
i486
i386
100
80286 10
8086
Source: Intel 1
1975
1980
1985
1990
1995
2000
2005
2010
Projected
Courtesy, Intel

24. Moore’s law in Microprocessors
1000
2X growth in 1.96 years!
100 10 P6
Pentium® proc
Transistors (MT) 1
486
386
0.1
286
Transistors on Lead Microprocessors double every 2 years
8086
8085
0.01
8080
8008
4004
0.001
1970
1980
1990
2000
2010
Year
Courtesy, Intel

25. Die size grows by 14% to satisfy Moore’s Law
Die Size Growth
100 P6
Pentium ® proc
Die size (mm)
486 10
386
286
8080
8086
8085
~7% growth per year
8008
~2X growth in 10 years
4004 1
1970
1980
1990
2000
2010
Year
Die size grows by 14% to satisfy Moore’s Law
Courtesy, Intel

26. Lead Microprocessors frequency doubles every 2 years
10000
Doubles every 2 years
1000 P6
100
Pentium ® proc
Frequency (Mhz)
486 10
386
8085
8086
286 1
8080
8008
4004
0.1
1970
1980
1990
2000
2010
Year
Lead Microprocessors frequency doubles every 2 years
Courtesy, Intel

27. Lead Microprocessors power continues to increase
Power Dissipation
100 P6
Pentium ® proc 10
486
286
Power (Watts)
8086
386
8085 1
8080
8008
4004
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
Courtesy, Intel

28. Power will be a major problem
100000
18KW
5KW
10000
1.5KW
1000
500W
Pentium® proc
Power (Watts)
100
286
486
8086 10
386
8085
8080
8008 1
4004
0.1
1971
1974
1978
1985
1992
2000
2004
2008
Year
Power delivery and dissipation will be prohibitive
Courtesy, Intel

29. Power density too high to keep junctions at low temp
10000
Rocket
Nozzle
1000
Nuclear
Reactor
Power Density (W/cm2)
100
8086 10
Hot Plate
4004 P6
8008
8085
386
Pentium® proc
286
486
8080 1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low temp
Courtesy, Intel

30. Not Only Microprocessors
Analog
Baseband
Digital Baseband
(DSP + MCU)
Power
Management
Small
Signal RF RF
Cell Phone
Digital Cellular Market
(Phones Shipped)
Units 48M 86M 162M 260M 435M
(data from Texas Instruments)

31. Challenges in Digital Design
µ DSM
µ 1/DSM
“Microscopic Problems”
• Ultra-high speed design
Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
Everything Looks a Little Different
“Macroscopic Issues”
• Time-to-Market
• Millions of Gates
• High-Level Abstractions
• Reuse & IP: Portability
• Predictability
• etc.
…and There’s a Lot of Them! ?

32. Complexity outpaces design productivity
Productivity Trends
Logic Transistor per Chip
(M)
10,000,000
10,000
1,000
100 10 1
0.1
0.01
0.001
100,000,000
0.01
0.1 1 10
100
1,000
10,000
100,000
Logic Tr./Chip
1,000,000
10,000,000
Tr./Staff Month.
100,000
1,000,000
Complexity
58%/Yr. compounded
10,000
(K) Trans./Staff - Mo.
Productivity
100,000
Complexity growth rate
1,000
10,000 x x
100
1,000 x x
21%/Yr. compound x x x
Productivity growth rate x 10
100 1 10
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
Source: Sematech
Complexity outpaces design productivity
Courtesy, ITRS Roadmap

33. Why Scaling? Technology shrinks by 0.7/generation
With every generation can integrate 2x more functions per chip; chip cost does not increase significantly
Cost of a function decreases by 2x
But …
How to design chips with more and more functions?
Design engineering population does not double every two years…
Hence, a need for more efficient design methods
Exploit different levels of abstraction

34. Design Abstraction Levels (black box)
SYSTEM
MODULE +
GATE
CIRCUIT
DEVICE G S D n+ n+
Cells are reused as much as possible to reduce the design effort
and to enhance the chances for a first-time-right implementation.
‘DESIGN COMPLEXITY’ can be reduced.

35. The crucial concept here is abstraction.
At each design level, the internal details of a complex module can be abstracted away and replaced by a black box view or model. This model contains virtually all the information needed to deal with the block at the next level of hierarchy. For all purposes, it can hence be considered a black box with known characteristics. As there exists no compelling need for the system designer to look inside this box, design complexity is substantially reduced.
For instance, an AND gate is adequately described by its Boolean expres-
sion (Z = A.B), its bounding box, the position of the input and output terminals, and the delay between the inputs and the output.
This is analogous to a software designer using a library of software routines such as input/output drivers. Someone writing a large program does not bother to look inside those library routines. The only thing he cares about is the intended result of calling one of those modules.
(CAD) frameworks for digital integrated circuits; without it the current design complexity would not have been achievable. Design tools include simulation at the various complexity levels, design verification, layout generation, and design synthesis.

36. The preceding analysis demonstrates that design automation and modular design practices have effectively addressed some of the complexity issues incurred in contemporary digital design. This leads to the following pertinent question. If design automation solves all our design problems, why should we be concerned with digital circuit design at all?
Will the next-generation digital designer ever have to worry about transistors or parasitics, or is the smallest design entity he will ever consider the gate and the module?
The truth is that the reality is more complex, and various reasons exist as to why an insight into digital circuits and their intricacies will still be an important asset for a long time to come :

37. • First of all, someone still has to design and implement the module libraries. Semiconductor technologies continue to advance from year to year. Until one has developed a fool-proof approach towards “porting” a cell from one technology to another, each change in technology—which happens approximately every two years—requires a redesign of the library.
• Creating an adequate model of a cell or module requires an in-depth understanding of its internal operation. For instance, to identify the dominant performance parameters of a given design, one has to recognize the critical timing path first.

38. • The library-based approach works fine when the design constraints (speed, cost or power) are not stringent. Unfortunately for a large number of other products such as microprocessors, success hinges on high performance, and designers therefore tend to push technology to its limits. At that point, the hierarchical approach tends to become somewhat less attractive. To resort to our previous analogy to software methodologies, a programmer tends to “customize” software routines when execution speed is crucial; compilers—or design tools—are not yet to the level of what human sweat or ingenuity can deliver.
• Even more important is the observation that the abstraction-based approach is only correct to a certain degree. The performance of, for instance, an adder can be substantially influenced by the way it is connected to its environment. The interconnection wires themselves contribute to delay as they introduce parasitic capacitances, resistances and even inductances. The impact of the interconnect parasitics is bound to increase in the years to come with the scaling of the technology.

39. • Scaling tends to emphasize some other deficiencies of the abstraction-based model. Some design entities tend to be global or external. Examples of global factors are the clock signals, used for synchronization in a digital design, and the supply lines. Increasing the size of a digital design has a profound effect on these global signals. For instance, connecting more cells to a supply line can cause a voltage drop over the wire, which, in its turn, can slow down all the connected cells. Issues such as clock distribution, circuit synchronization, and supply-voltage distribution are becoming more and more critical. Coping with them requires a profound understanding of the intricacies of digital circuit design.

40. • Another impact of technology evolution is that new design issues and constraints tend to emerge over time. A typical example of this is the periodical reemergence of power dissipation as a constraining factor, as was already illustrated in the historical overview. Another example is the changing ratio between device and interconnect parasitics. To cope with these unforeseen factors, one must at least be able to model and analyze their impact, requiring once again a profound insight into circuit topology and behavior.
• Finally, when things can go wrong, they do. A fabricated circuit does not always exhibit the exact waveforms one might expect from advance simulations. Deviations can be caused by variations in the fabrication process parameters, or by the inductance of the package, or by a badly modeled clock signal. Troubleshooting a design requires circuit expertise.

41. Design Metrics
How to evaluate performance of a digital circuit (gate, block, …)?
Cost
Reliability (Noise)
Scalability
Speed (delay, operating frequency of micro processors)
Power dissipation
Energy to perform a function (mobiles)

42. Cost of Integrated Circuits
NRE/fixed (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor, independent of the sales volume, the number of products sold
Recurrent costs/variable
silicon processing, packaging, test
proportional to products volume
proportional to chip area

43. NRE Cost is Increasing

44. Die Cost Single die Wafer Going up to 12” (30cm)
From

45. Cost per Transistor
cost:
¢-per-transistor 1
Fabrication capital cost per transistor (Moore’s law)
0.1
0.01
0.001
0.0001
1982
1985
1988
1991
1994
1997
2000
2003
2006
2009
2012

46. Yield

47. Defects a is approximately 3
The smaller the gate, the higher the integration density and the smaller the die size.
Smaller gates furthermore tend to be faster and consume less energy, as the total gate capacitance which is one of the dominant performance parameters often scales with the area.

48. Some Examples (1994) Chip Metal layers Line width Wafer cost Def./ cm2
Area mm2
Dies/wafer
Yield
Die cost
386DX 2
0.90
$900
1.0 43
360
71% $4
486 DX2 3
0.80
$1200 81
181
54%
$12
Power PC 601 4
$1700
1.3
121
115
28%
$53
HP PA 7100
$1300
196 66
27%
$73
DEC Alpha
0.70
$1500
1.2
234 53
19%
$149
Super Sparc
1.6
256 48
13%
$272
Pentium
1.5
296 40 9%
$417

49. Reliability― Noise in Digital Integrated Circuitsv ( t ) V DD i ( t )
Inductive coupling
Capacitive coupling
Power and ground
noise

50. DC Operation Voltage Transfer Characteristic
V(x)
V(y) V OH OL M IH IL f
V(y)=V(x)
Switching Threshold
Nominal Voltage Levels
VOH = f(VOL)
VOL = f(VOH)
VM = f(VM)

51. Mapping between analog and digital signalsV IL IH in
Slope = -1 OL OH
out V “ 1 ” OH V IH
Transition
Width (TW)
Undefined
Region V IL “ ” V OL

52. Definition of Noise Margins
Robust, insensitive to
noises
"1" V OH
Noise margin high NM H V IH
Undefined Region NM V L
Noise margin low IL V OL
"0"
Gate Output
Stage M
Gate Input
Stage M+1

54. Regenerative Property1 2 3 4 5 6
Regenerative
Non-Regenerative
After passing a no. of stages
The difference is due to the gain char. Of gates

55. Regenerative Property1 2 3 4 5 6
A chain of inverters
Simulated response

56. A gate has Regenerative property
VTC should have a transient region with gain greater than 1, bordered by two legal zones where the gain should be less than 1. V IL IH in
Slope = -1 OL OH
out

57. Fan-in and Fan-out N
Fan-out N M
Fan-in M

58. The Ideal Gate R = ¥ R = 0 Fanout = ¥ NMH = NML = VDD/2 g =  V V i oin

59. An Old-time Inverter (V) out V 5.0 NM 4.0 3.0 2.0 V NM 1.0 0.0 1.0 2.0H
1.0
0.0
1.0
2.0
3.0
4.0
5.0 V
(V) in

60. VOH=3. 5 V ; VOL = 0. 45 V VIH = 2. 35 V ; VIL = 0. 66V VM= 1
VOH=3.5 V ; VOL = 0.45 V VIH = 2.35 V ; VIL = 0.66V VM= 1.64 V ; NMH = 1.15 V ; NML = 0.21 V

61. Delay Definitions
tp: propagation
delay of gate
tp= (tpHL+tpLH)/2

62. Assignment-1 (due on August 10th)
tp= (tpHL+tpLH)/2
Find the propagation delay of an inverter
PMOS: W=15u L=2.5u ; NMOS: W=5u L=2.5u
- Vdd=5Volts
Input at the gate is a pulse with following specifications:
initial voltage=0; peak voltage=5 V; initial delay time=0; rise time=5ns;
fall time=5ns; pulse-width=48ns; and Period=120ns,
Consider Level 2 MOSFET model
Consider load capacitance CL=100 fF at the output.
Submit your assignments via to:

63. A First-Order RC Networkv
out in C R
tp = ln (2) t = 0.69 RC
Important model – matches delay of inverter
The time to reach the 50% point is easily computed as t = ln(2) t = 0.69 t. Similarly, it takes t= ln(9) t = 2.2 t to get to the 90% point.

64. Power Dissipation Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)
Peak power (supply line size):
Ppeak = Vsupplyipeak
Average power (Battery Size):
Pave : Static and Dynamic

65. Energy and Energy-Delay
Power-Delay Product (PDP) = E = Energy per operation = Pav  tp
The PDP is simply the energy consumed by the gate per switching event.
Energy-Delay Product (EDP) = quality metric of gate = E  tp

66. A First-Order RC Networkv
out v in CL

67. Summary
Digital integrated circuits have come a long way and still have quite some potential left for the coming decades
Some interesting challenges ahead
Getting a clear perspective on the challenges and potential solutions is the purpose of this book
Understanding the design metrics that govern digital design is crucial
Cost, reliability, speed, power and energy dissipation