1. Conditional Signal Assignment

2. Let’s consider a Priority Encoder - PENC
Let’s consider a Priority Encoder - PENC. Usually a PENC has 2n inputs and n outputs. It determines the index of the active input. For example, an input is active if it is ‘0’-logic.
If the number of inputs is four and their values are:
i0 i1 i2 i3 ,
then i2 is the only active input, so the output must be 210=0102.

3. What if the inputs are
i0 i1 i2 i3 , or ?
Clearly, an additionally rule is necessary:
If there are many active inputs, the PENC will output the smallest index from the indices of the active inputs. This is the software interpretation!

4. The smallest index rule determines a priority structure: smaller the index of an input, greater the priority of that input.
For the inputs
i0 i1 i2 i3 ,
the output is 110=0012
and for the inputs:
the output is 010=0002
Concluding, a PENC outputs the index of the highest priority ACTIVE input. This is the hardware interpretation!
PENCs are used in interrupt systems.

5. The truth table is large enough – 16 lines.
The truth table for a PENC4 is:
i0 i1 i2 i3 c1 c0
? ?
The truth table is large enough – 16 lines.
How large would be the truth table for a PENC8?
256 lines!
Selected signal assignment doesn’t work too well!

6. The truth table for a PENC4 is:
i0 i1 i2 i3 c1 c0
? ?
≡ i0 i1 i2 i3 c1 c0
0 x x x 0 0
1 0 x x 0 1
x 1 0
? ?
How would you implement this in C?
if (i0==0) c=00;
else if (i1==0) c=01;
else if (i2==0) c=10;
else c=11;

7. Conditional signal assignment:
Similar to if-then-elseif-then-elseif- ….else in C.
Syntax:
target_signal <= expression1 when bcond1 else
expression2 when bcond2 else
• • •
expressionN when bcondN else
expressionN+1;
Target_signal can be scalar or composite.
A signal is assigned expression1 if the boolean condition bcond1 is met. Otherwise, the next condition after the else clause is checked, etc.
If no condition is met, expressionN+1 is assigned.
Conditions may overlap.
Any else is optional. There can be no else.

8. PENC4: Entity PENC4 is Port ( iaI : in std_logic_vector (3 downto 0);
oAct : out std_logic; -- Active
oaC : out std_logic_vector (1 downto 0) );
end;
architecture a of PENC4 is
Begin
oaC <= “00” when iaI(0)=‘0’ else
“01” when iaI(1)=‘0’ else
“10” when iaI(2)=‘0’ else
“11”;
oAct <= ‘1’ when iaI/=“1111” else ‘0’; i0 i1 i2 i3 c1 c0 x 1 ?

9. Exercises -1
Using only parallel statements, write the VHDL code for a combinational circuit whose input is a 4-bit vector. The circuit’s output is ‘1’ when the two halves of the vector are complementary and ‘0’ otherwise.
For example, if the input is “1100” the output will be ‘1’ because NOT “11” = “00”. If the input is “1010” the output will be ‘0’ because NOT “10” ≠ “10”.

10. For A=”001” and B=”001” the output will be ‘0’.
Exercises - 2
Using only parallel statements, write the VHDL code for a combinational circuit whose input consists of two one-dimensional arrays, A and B. The length of each array is 3-bit.
The circuit’s output is ‘1’ when the value of A is the mirror image of B’s value (A’s value read from left to right equals the value of B read from right to left).
For example, if A=”110” and B=”011” the output ‘1’ because A read from left to right is ‘1’, ‘1’, ‘0’ and B read from right to left is also ‘1’, ‘1’, ‘0’.
For A=”001” and B=”001” the output will be ‘0’.

11. Exercises – 3
Using only parallel statements, slices and concatenation, write the VHDL code for a combinational circuit which rotates left its input.
iaD(7 downto 0) is the input vector.
iaN(3 downto 0) specifies the number of rotations
oaY(7 downto 9) is the output vector.