1. Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu
Engineering 43
Diodes-2
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer

2. Skip for 09May17 Meeting Learning Goals
Understand the Basic Physics of Semiconductor PN Junctions which form most Diode Devices
Sketch the IV Characteristics of Typical PN Junction Diodes
Use the Graphical LOAD-LINE method to determine the “Operating Point” of Nonlinear (includes Diodes) Circuits
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3. Skip for 02May17 Meeting Learning Goals
Analyze diode-containing Voltage-Regulation Circuits
Use various math models for Diode operation to solve for Diode-containing Circuit Voltages and/or Currents
Learn The difference between LARGE-signal and SMALL-Signal Circuit Models
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IDEAL and PieceWise-Linear Models

4. Diode Models
LoadLine Analysis works well when the ckt connected to a SINGLE Diode can be “Thevenized”
However, for NONLinear ckts, such as those containing multiple diodes, construction of the LOAD-Curve Eqn may be difficult, or even impossible.
Many such ckts can be analyzed by Idealizing the diode

5. Diode Models Consider an Electrical Diode →
Anode
Diode Models V I
Consider an Electrical Diode →
We can MODEL the V-I The Didode Rectifying behavior in Several ways
Recall 𝑑I 𝑑V=G= 1 R
Cathode
IDEAL Model
LINEAR Model
REAL Behavior
OFFSET Model
𝑑I 𝑑V V=0=∞
𝑑I 𝑑V Vknee=∞
𝑑I 𝑑V Vknee≅ ∆I ∆V ∆I
Mr. Phillips described the linear model as the KNEE Voltage-Offset plus Rb = delV/delI ∆V
knee
knee

6. Ideal Model (Ideal Rectifier)
Diode ON
Diode OFF
Analyze Ckts containing Ideal Diodes
Assume (or Guess) a “state” for each diode. Ideal Diodes have Two states
ON → a SHORT Ckt when Fwd Biased
OFF →an OPEN Ckt if Reverse Biased
Check the Assumed Opens & Shorts
Should have Current thru the SHORTS
Should have ∆V across the OPENS

7. Ideal Model (Ideal Rectifier)
Diode ON
Diode OFF
Check to see if guesses for i-flow, ∆V, and BIAS-State are consistent with the Ideal-Diode Model
If i-flow, ∆V, and bias-V are indeed consistent with the ideal model, then We’re DONE.
If we arrive at even a SINGLE Inconsistency, then START OVER at step-1

8. Example  Ideal Diode Find For Ckt Below find:
Use the Ideal Diode Model
Define Node-A

9. Example  Ideal Diode In this Case VD1 = VD2 = 0
Thus D2 Anode is connected to GND
Then Find by Ohm
Next use KCL at Node-A (in = out)
D2 anode connected to GND thru D1, which as VD1 = 0, since it also conducts. This makes a “short” between GND and pt-A. The current on thru RHS of the KCL eqn is the current thru R1 • After RED line ask students “what is vo? ANS = ZERO
Assume BOTH Diodes are ON (Conducting)

10. Example  Ideal Diode Thus
Now must Check that both Diodes are indeed conducting
From the analysis
Thus the current thru both Diodes is positive which is consistent with the assumption 
Using ID2 = 1 mA

11. Example  Ideal Diode
Another way to think about this is that since VD2 = 0 and VD1 = 0 (by Short Assumption) Find Vo = GND+VD2−VD1 = GND + 0 − 0 = 0
Thus the Answer
Since both Diodes conduct the Top of Vo is connected to GND thru D2 & D1

12. Example  Ideal Diode Find For Ckt Below find:
Use the Ideal Diode Model
Note the different values on R1 & R2
Swapped

13. Example  Ideal Diode As Before VD1 = VD2 = 0
Again VB shorted to GND thru D1
Then Find by Ohm
Now use KCL at Node-B (in = out)
D2 cathode connected to GND thru D1, which as VD1 = 0, since it also conducts
Again Assume BOTH Diodes are ON, or Conducting

14. Example  Ideal Diode Thus
Now must Check that both Diodes are indeed conducting
From the analysis
We find an INCONSISTENCY and our Assumption is WRONG 
𝐼 𝑑2 = 10V 9.9kΩ =1.01 mA
𝐼 R1 = 10V 10kΩ =1 mA
Using ID2 = 1.01 mA

15. Example  Ideal Diode In this Case D1 is an OPEN → Id1 =0
Current Id2 must flow thru BOTH Resistors
Then Find by Ohm
Must Iterate
Assume
D1 → OFF D2 → ON

16. Example  Ideal Diode  By KVL & Ohm
Since the Anode Side of D1 is at GND, Then D1 is INDEED Reverse-Biased, so the Ckt operation is, indeed, Consistent with our Assumption
Must Check that D1 is REVERSE Biased as it is assumed OFF 

17. Example  Ideal Diode
D2 is ON → VD2 = 0 D1 is OFF → Current can only flow thru D2
In this case Vo = VB
By the Previous Calculation of VB Find
Calculate Vo by noting that:

18. Offset & Linear Models The Offset Model
Better than Ideal, but no account of Forward-Slope
The Linear Model
The model eqn:
Yet more accurate, but also does not account for Rev-Bias Brk-Down
Rb depends on the physical SIZE of the diode; specifically the Cross-Section of the PN jcn. Neither Model accounts for Rev-Bias BreakDown => Need to Add Another Line-Segment to these piecewise Linear Models.

19. Point Slope Line Eqn
When constructing multipiece-wise linear models, the Point-Slope Equation is extremely Useful
Where
(x1, y1) & (x2, y2) are KNOWN Points
Example: Find Eqn for line-segment:
(3,17)
(19,5)
MATLAB Session in Command Window → x =[3, 19]; y = [17,5]; plot(x,y, 'd', x,y, 'LineWidth',3), grid, xlabel('x'), ylabel('y')

20. Point Slope Line Eqn Using the 2nd Point
Can easily convert to y = mx+b
Multiply by m, move −5 to other side of =
(3,17)
(19,5)

21. Slopes on vi Curve
With Reference to the Point-Slope eqn v takes over for x, and conversely i takes over for y
The Slope on a vi Curve is an A/V Conductance
If the curve is NONlinear then the local conductance is the first Derivative
Recall the Op-Pt is also the Q-Pt
Mr. Phillips talked about the small-signal transconductance in the MOSFET Lab

22. Slopes on vi Curve
Finally recall that conductance & resistance are Inverses
Example: Find the RESISTANCE of the device associated with the VI curve that follows Δ𝐼 Δ𝑉
V =[3, 19]; I = [17,5]; plot(x,y, 'd', x,y, 'LineWidth',3), grid, xlabel('V'), ylabel('I'), title('Linear VI Curve')

23. Slopes on vi Curve Since R = 1/G Find the Device Resistance as
For a NONlinear vi curve the local slope then: r = 1/g
The General Reln

24. Example PieceWise Linear Model
Construct a PieceWise Linear Model for the Zener vi curve shown at Right

25. PieceWise Linear Zener
Us Pt-Slp eqn with (0.6V,0mA) for Pt-1
Segment- B is easy
m for Segment A

26. PieceWise Linear Zener
Us Pt-Slp eqn with (−6V,0mA) for Pt-1
Thus the PieceWise Model for the Zener
m for Segment C

27. Example PieceWise Linear Model
Alternatively in terms of Resistances
ADVICE: remember the Pt-Slope Line-Eqn

28. Half-Wave Rectifier Ckt
Consider a Sinusoidal V-Source, such as an AC socket in your house, supplying power to a Load thru a Diode
0.7 is the OffSet, or Knee voltage
Power Input
Load Voltage

29. HalfWave Rectifier
Note that the Doide is FWD-Biased during only the POSITIVE half-cycle of the Source
Using this simple ckt provides to the load ONLY positive-V; a good thing sometimes
However, the positive voltage comes in nasty PULSES which are not well tolerated by positive-V needing loads

30. Smoothed HalfWave Rectifier
Adding a Cap to the Circuit creates a Smoothing effect
In this case the Diode Conducts ONLY when vs>vC
and vC=vL
This produces vL(t) and iL(t) curves
Note that iL(t) is approx. constant
Slope STEEPEST Here
Slope = 0 Here
Recall the Caps Resist Voltage-Changes across them. Vr is the RIPPLE Voltage

31. Smoothed HalfWave Rectifier
The change in Voltage across the Cap is called “Ripple”
Often times the load has a Ripple “Limit” from which we determine Cap size
From the iL(t) curve on the previous slide note:
Cap Discharges for Almost the ENTIRE Cycle time, T (diode Off)
The Load Current is approx. constant, IL
Recall from EARLY in the Class
Ripple

32. Smoothed HalfWave Rectifier
Also from Cap Physics (chp3)
In the Smoother Ckt the Cap charges during the “Ripple” portion of the curve
Equating the Charge & Discharge “Q’s find
Note that both these equations are Approximate, but they are still useful for initial Ckt Design
Solving the equations for the Cap Value needed for a given Vr
Charge
Discharge

33. Smoothed HalfWave Rectifier
Find the Approximate Average Load Voltage
VL,hi
VL,lo

34. Capacitor-Size Effect
Any load will discharge the capacitor. In this case, the output will depend on how the RC time constant compares with the period of the input signal.
The plots at right consider the various cases for the simple circuit above with a 1kHz, 5V sinusoidal input

35. Full Wave Rectifier
Current path for
Negative half-cycle
The HALF-WAVE ckt will take an AC-Voltage and convert it to DC, but the rectified signal has gaps in it.
The gaps can be eliminated thru the use of a Full-Wave Rectifier Circuit
+10V
−10V
The Diodes are
Face-to-Face (right)
Tail-to-Tail (left)
This rectified output has NO Gaps
The current path goes thru the GND symbols

36. Beware GND Grouping

37. Full Wave Rectifier Operation
D1 Supplies V to Load D2 Returns Current to Src
D4 Supplies V to Load D3 Returns Current to Src
Explain that transformer merely reduces the amplitude of the sinusoidal signal. The current makes its way back to the source thru the GND connections

38. Full Wave Rectifier Smoothing
The Ripple on the FULL wave Ckt is about 50% of that for the half-wave ckt
Since the Cap DIScharges only a half-period compared to the half-wave ckt, the size of the “smoothing” cap is then also halved:

39. START HERE on 09May17 Game Plan
Finish ENGR-43_Lec-10b_Sp17_Diode-2_SmallSignalAnalysis.pptx (this file)
Complete as much as possible in
ENGR-43_Lec-12a_Sp17_FETs-1_Construction_viCurve.pptx
ENGR-43_Lec-12b_Sp1y_FETs-2_LoadLine_Analysis.pptx
ENGR-43_Lec-12c_Sp16_FETs-3_MOSamps_MOSgates.pptx

40. Small Signal Models
Often we use NonLinear Circuits to Amplify, or otherwise modify, non-steady Signals such as ac-sinusoids that are small compared to the DC Operating Point, or Q-Point of the Circuit.
Over a small v or i range even NonLinear devices appear linear. This allows us to construct a so-called Small Signal Linear Model

41. Small Signal Analysis
Small signal Analysis is usually done in Two Parts:
Large-Signal DC Operating Point (Q-Pt)
Linearize about the Q-Pt using calculus
Recall from Calculus & ENGR25
This approximation become more accurate as ∆y & ∆x become smaller
This how SPICE works

42. Small Signal Analsyis Now let 𝑦→ 𝑖 𝐷 and 𝑥→ 𝑣 𝐷
Use a DC power Supply to set the operating point on the diode curve as shown at right
This could be done using LoadLine methods
From Calculus
Next Take derivative about the Q-Pt

43. Small Signal Analysis About Q-Pt
Now if we have a math model for the 𝑣𝑖 curve, and we inject ON TOP of VDQ a small signal, ∆vD find
The derivative is the diode small-signal Conductance at Q

44. Small Signal Analysis In the large signal Case: R = 1/G
By analogy in the small signal case:
r = 1/g
Also since small signal analysis is associated with small amounts that change with time…
Define the Diode’s DYNAMIC, small-signal Conductance and Resistance
𝐹𝑜𝑟 𝑑𝑣 𝐷 𝑑𝑖 𝐷

45. Small Signal Analysis Note Units for rd Recall the approximation ∆ 𝑖 𝐷
Change Notation for Small Signal conditions
Find 𝑟 𝑑 for a “Shockley” Diode in majority FWD-Bias
Recall Shockley Eqn
Then the Large-signal Operating Point at 𝑣 𝐷 = 𝑉 𝐷𝑄
The last approximation is for significant FWD bias → VDQ >> nVT

46. Small Signal Analysis Taking the derivative of the Shockely Eqn
Recall from last sld
Sub this Reln into the Derivative Eqn
Recall
Subbing for 𝑑𝑖 𝐷 𝑑𝑣 𝐷
The last approximation is for significant FWD bias → VDQ >> nVT

47. Notation: Large, Small, Total
𝑉 𝐷𝑄 and 𝐼 𝐷𝑄 are the LARGE Signal operating point (Q-Pt) DC quantities
These are STEADY-STATE values
𝑣 𝐷 and 𝑖 𝐷 are the TOTAL and INSTANTANEQOUS quantities
These values are not necessarily steady-state. To emphasize this we can alternatively write 𝑣 𝐷 𝑡 ) and 𝑖 𝐷 𝑡

48. Notation: Large, Small, Total
𝑣 𝑑 and 𝑖 𝑑 are the SMALL, AC quantities
These values are not necessarily steady-state. To emphasize this we can write 𝑣 𝑑 𝑡 and 𝑖 𝑑 𝑡
An Example for Diode Current notation →

49. Effect of Q-Pt Location
From Analysis
Steeper Slope
UNequal-amplitude current signals
Steep Slope
Same id, but different vd’s result from the location of the Q-point and rd calculation
STEEPER Slopes produce Greater AMPLIFICATION

50. DC Srcs  SHORTS in Small-Signal
In the small-signal equivalent circuit DC voltage-sources are represented by SHORT CIRUITS; since their voltage is CONSTANT, they exhibit ZERO INCREMENTAL, or SIGNAL, voltage
That is well designed DC voltage/current sources are absolutely Constant.
Thus they ABSORB small signals, which then appear as GROUND to these signals
In the Small Signal Regime both “Rails” are regarded as grounds.

51. Setting 𝑸, Injecting 𝒗 Consider this ckt with AC & DC V-srcs Sets 𝑉 𝑄
Note the coupling capacitor: Zc = i/(jwC)
Sets 𝑣 𝑑

52. Large and Small Signal Ckts
Recall from Chps 3 and 5 for Caps:
OPENS to DC
SHORTS to fast AC
Thus if C1 is LARGE it COUPLES 𝑣 𝑖𝑛 𝑡 to the rest of the ckt
Similarly, Large C2 couples 𝑣 𝑜 𝑡 to the Load Resistor, 𝑅 𝐿
To Find the 𝑄 -point DEcouple 𝑣 𝑖𝑛 and 𝑣 𝑜 to arrive at the DC circuit
𝑉 𝐷 = 𝑉 𝑄

53. Large and Small Signal Ckts
Finding the Large signal Model was easy; the Caps act as OPEN Ckts
The Small Signal Ckt requires more work
Any DC V-Supply is a SHORT to GND
The Diode is replaced by 𝑟 𝑑 (or 𝑔 𝑑 )
The Caps are Shorts
Thus the Small Signal ckt for the above

54. Example: Small Signal Gain
Find the Small Signal Voltage Amplification (Gain), Av, of the previous circuit
Using the Small Signal Circuit
Note that 𝑅 𝐿 , 𝑟 𝑑 , and 𝑅 𝐿 are in Parallel
And 𝑣 𝑜 𝑡 appears across this parallel combination
The equivalent ckt

55. Example: Small Signal Gain
Thus for this Ckt the Large, Small, and small-Equivalent ckts
Then the Amplification (Gain) by Voltage Divider

56. Small Signal BJT Amp All Done for Today Common Collector Amplifier
LARGE
Signal Model
All Done for Today
Small Signal BJT Amp
Common Collector Amplifier
SMALL
Signal Model

57. Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu
Engineering 43
Appendix
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer

59. Small Signal Analysis In the large signal Case: R = 1/G
By analogy In the small signal case:
r = 1/g
Also since small signal analysis is associated with small amounts that change with time…
Define the Diode’s DYNAMIC Conductance and Resistance

60. P10.67
Graph vo vs. vi for vi: −5Vdc to +5Vdc

65. Beware The Ground Grouping

66. Beware GND Grouping

67. Beware GND Grouping