1. Stefano Levorato INFN Trieste
MPGD-dedicated HV system TASK 6
MPGD dedicated HV system
TASK COORDINATOR: S. Levorato
PARTICIPANTS: INFN – Trieste
3/23/2017 MPGD_NEXT
Stefano Levorato INFN Trieste

2. Stefano Levorato INFN Trieste
MPGD-dedicated HV system TASK Goal of the Project
Main goal is to match the HV requirements not commercially available for the MPGD needs
true real-time monitoring of the main parameters (voltage, current)
the fast control of the HV channels (related to the next point)
the use of local intelligence for the application of feedback protocols when pre-breakdown conditions are detected, useful for systems where the large number of HV channels increases the monitor and control complexity of the system
HV generated at the detector level: HV cabling, connectors, space constrains, cost, accumulated charge issues
Modularity of the system: large size projects employing MPGDs may use a large number of channels (M/S architecture)
Compactness
3/23/2017 MPGD_NEXT
Stefano Levorato INFN Trieste

3. Stefano Levorato INFN Trieste
MPGD-dedicated HV system TASK Goal of the Project
By combining commercially available devices as well as custom made the foreseen performance figures to achieve:
Time stamp resolution for current and voltage monitoring in the order of 10 ns or better
High resolution voltage monitoring better than 0.5 Volt on several kVolt scale at sampling rate > 100 kHz
Precise current monitoring at the level of 10 pA at sampling rate > 100 kHz
On board logic for decisional operation on predefined scheme as well as warning on “interesting” events to the user: two mode systems 1) normal monitoring with relaxed separation between consecutive time stamps 2) very fine monitoring info in case of non standard events
The main innovative features are:
true real-time monitoring
A tool to perform MPGD R&D: by the detailed time-stamped information, understand the precise evolution of the break-down events
HV generated at the detector level
Reduced size: each HV unit ~ 30 cm x 20 cm x 5 cm
Applications:
MPGD characterization studies
Powering of large-size MPGD systems
3/23/2017 MPGD_NEXT
Stefano Levorato INFN Trieste

4. Stefano Levorato INFN Trieste
MPGD-dedicated HV system TASK Activities
Three main activities performed / on-going
Selection of the DC to DC converter (Commercial device)
ADC Board FMC standard adopted,
the custom-made Pico ammeter (Custom made)
Carrier (Commercial)
3/23/2017 MPGD_NEXT
Stefano Levorato INFN Trieste

5. Stefano Levorato INFN Trieste
MPGD-dedicated HV system TASK DC-DC units
EMCO
Q60-5R ( Vin = 0 to +5V, Vout = 0 to +6kV/0.5W )
Q60N-5R ( Vin = 0 to +5V, Vout = 0 to -6kV/0.5W )
A60P-5 ( Vin = 0 to +5V, Vout = 0 to +6kV/1W )
A60N-5 ( Vin = 0 to +5V, Vout = 0 to -6kV/1W )
AG60P-5 ( SMD, Vin = 0 to +5V, Vout = 0 to +6kV/1W )
AG60N-5 ( SMD, Vin = 0 to +5V, Vout = 0 to -6kV/1W)
ISEG
BP040105n12
PCB-HV-module of 4W BPS series ( now available also up to 6 kV)
Vout = 0 to -4 kV / Ioutnom = 1 mA / Vin = 11,5 to 15,5 V-DC
Vremote/mon= 0 to 5 V / V-Imon = 0 bis 5 V / Vref = 5 V
Ripple & noise < 40 mVpp at full load
BP020205p12
PCB-HV-module BPS series (4 W)
Vout = 0 to +2 kV / Iout max = 2 mA / Vin = 11,5 to 15,5 V-DC
Ripple & noise < 20 mVp-p at full load
100MΩ load
measurements performed:
Output HV vs analog setting
Ripple characteristics
selected
3/23/2017 MPGD_NEXT
Stefano Levorato INFN Trieste

6. Stefano Levorato INFN Trieste
MPGD-dedicated HV system TASK ADC Board and the custom-made Picoammeter
Discharge evolution time has driven the choice of the ADC Chip
Capability to detect fast transients (time resolution: ~2ns)
ADC selected:
8-Bit 500 MSPS A/D Converter ADC08500
The ADC board (custom design, built and successfully tested):
ADC self-calibration
multiple ADC synchronization capability
Low-Pin-Count FMC connector
5 ns time division
Current measurement via custom built Picoammeter (OPA in transconductance)
It will host the DC/DC converter and the PA
( Analog/Digital Separation)
3/23/2017 MPGD_NEXT
Stefano Levorato INFN Trieste

7. Stefano Levorato INFN Trieste
MPGD-dedicated HV system TASK carrier in FMC standard
Zed Board based on hybrid Xilinx Zynq
commercial carrier including high throughput low-pin-count FMC
Fully Programmable System-on-Chip (SoC) device
combining a ‘hard’ dual core ARM processor with an FPGA fabric
dual-core ARM Cortex-A9 processor,
Programmable Logic: FPGA Artix-7 or Kintex-7 fabric
STATUS
First design project started in VHDL code successfully tested
the external ADC is managed:
providing the LVDS clock signals for data conversion and reading in slave mode the ADC data
writing the continuous ADC data stream into a FIFO memory for its transmission to the PS of the Zynq device, which in time is in charge of its retransmission to a PC
ADC read at maximum speed of 500 MSPS confirming the correct choice of the FMC Carrier FPGA/processor
A general purpose communication protocol (GPCP) is being developed to be used
PC software and from the ARM processor software : already reading and writing
memory blocks into the ARM processor from PC
The PC resident software is being developed in PyQT (Python-QT) Elementary GUI already
developed to send and receive blocks of data to/from the Zynq device
3/23/2017 MPGD_NEXT
Stefano Levorato INFN Trieste