Introduction to Field Programmable Gate Arrays FPGAs

Introduction to Field Programmable Gate Arrays FPGAs
4/24/2018 Introduction to Field Programmable Gate Arrays FPGAs John Coughlan Technology Department

Outline Q. What does FPGA stand for? FPGA Architecture
4/24/2018 Q. What does FPGA stand for? FPGA Architecture Common characteristics Specialised blocks FPGA Design Flow Hardware Description Languages Design Tools FPGAs Applications Particle Physics Computing Trends and Future of FPGAs ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

What does FPGA stand for?
4/24/2018 Field Programmable Gate Array Field : “in the field” Programmable : “Re-Configurable” Change Logic Functions Gate Array : reference to ASIC internal architecture A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

What is an FPGA? Field Programmable Gate Array
4/24/2018 Field Programmable Gate Array (Very) Large Scale Integrated Circuit Digital Logic Programmed after manufacture rather than unchangeable Application Specific Integrated Circuit ASIC First appeared in 1980’s. Took off in last decade. Standard IC manufacturing process Following Moore’s Law

Why are they of Interest?
4/24/2018 Essential Components in modern HEP Electronics (& Industry!) Data Acquisition (Millions Channels) Triggers Computer Interfaces VME ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

What is an FPGA? Field Programmable Gate Array
4/24/2018 Field Programmable Gate Array Configurable (Programmable) General Logic Blocks Configurable Interconnects Plus Special Purpose Blocks (Embedded Processors) Configured (multiple times) to perform variety of tasks (HEP) Simple Logic Block ‘Islands’ in a ‘Sea’ of Interconnects 10,000 … 100,000+ (Massively Parallel HEP) A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

Little bit of History… 4/24/2018 FPGAs appeared in the 1980’s. Took off in last decade. Bridge gap between simple Programmable Logic and semi custom ASICs (Application Specific Integration Circuits). A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

Previous Generations Logic Devices
4/24/2018 Simple Logic (used to “glue” other ICs together) Reprogrammable (UV light, electrically eraseable) Cheap Easy to Program Many different variations Eg. Implement Logic as ‘Sum of Products’ Terms A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

Little bit of History… 4/24/2018
A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

ASICs Large Complex Functions
4/24/2018 Large Complex Functions Customised for Extremes of Speed, Low Power, Radiation Hard (HEP) (Very) Expensive (in small 90 nm ~ $1M mask set (Very) Hard to Design. Long Design cycles. Not Reprogrammable. High Risk Semi Custom Gate Arrays. A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

FPGAs best of both worlds…
4/24/2018 Large Complex Functions Programmability, Flexibility. Massively Parallel Architecture Fast Turnaround Designs Mass produced. Cheap Prototype ASICs Power Hungry A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

Common FPGA Characteristics
4/24/2018 Logic Elements Lookup Table Flip Flops Multiplexers Memory Resources SRAM blocks Routing Resources Hierarchy Programmable Channels between Logic Elements Configurable I/O Interfaces to the real world. Logic Levels. Fast Serial I/O Massively Parallel Architecture (HEP) Clocked Logic Design CMOS based using SRAM cells for configuration FPGAs come in a wide variety of sizes and with many different combinations of internal and external features. What they have in common is that they are composed of relatively small blocks of programmable logic. These blocks, each of which typically contains a few registers and a few dozen low-level, configurable logic elements, are arranged in a grid and tied together using programmable interconnections. In a typical FPGA, the logic blocks that make up the bulk of the device are based on lookup tables (of perhaps four or five binary inputs) combined with one or two single-bit registers and additional logic elements such as clock enables and multiplexers. These basic structures may be replicated many thousands of times to create a large programmable hardware fabric.

Logic Elements Lookup Table LUTs (Combinatorial Logic) Multiplexers
4/24/2018 Lookup Table LUTs (Combinatorial Logic) Multiplexers Flip-Flops (Clocked Registered Logic) Options configured by SRAM cells ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Memory SRAM blocks Data Buffers (HEP) FIFOs Code 4/24/2018
‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

System on a Chip Recently Embedded Micro-Processors in Fabric
4/24/2018 Recently Embedded Micro-Processors in Fabric Hard Cores e.g. RISC PowerPC Soft Cores Peripherals Timers, GPIO Run Operating System e.g. Linux Combine Micro-Processor & Massively Parallel Logic Dual Design Flows Firmware HDL Software C ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Input and Output Several hundred of I/O pins
4/24/2018 Several hundred of I/O pins All flavours of Logic Levels e.g. LVDS, TTL High Speed Serial Transceivers (up to 10? Gbps) (HEP) Ethernet MAC Cores ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Ethernet FPGA and PC Networks
4/24/2018 Ethernet MAC COREs inside FPGA Drive Data via Serialiser I/O and Optical Transceiver chip Direct to Network Card in PC. 2 IP Nodes on Network. Small DAQ systems Dev Board V2 Pro FPGA Rocket IO MGTs Prog’ Data Generator Gigabit Ethernet SFP Gb Opto Transceiver RAID 0 Quixtream ® UDP core Tx1 Tx2 PC Tx3 Gb NIC Tx4 Prog’ Data Generator Rx1 ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Trigger

Programming an FPGA Field Programmable Gate Array
4/24/2018 Field Programmable Gate Array Configurable (Programmable) General Logic Blocks Configurable Interconnects Bit File contains the Configuration Information A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

Programming (Configuring) an FPGA
4/24/2018 SRAM cells holding configuration are Volatile Memory Lose configuration when board power is turned off. Keep Bit Pattern describes the Logic Functions in non-Volatile Memory e.g. ROM or Compact Flash card Reprogramming takes ~ secs Uses JTAG Boundary Scan ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Design Flows High level Description of Logic Design
4/24/2018 High level Description of Logic Design Schematic Hardware Description Language Compile into Netlist. Low (Logic Gates) level description. Target Netlist to FPGA Fabric Mapping and Packing Placing and Routing Tools Generate the Bit File Simulation Timing Analysis ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Design Flows Schematic Capture of Logic Design. Useful at Top level.
4/24/2018 Schematic Capture of Logic Design. Useful at Top level. Create Netlist. Text file with signal connections. ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Hardware Description Languages
4/24/2018 Behavioural / Register Transfer Level Description Program Statements. Loops. If Statements …etc Describing Mixture of Combinatorial and Sequential Logic and Signals between. Engineers call it Firmware VHDL (VHSIC Hardware Description Language) Very High Speed Integrated Circuit VERILOG (US) Synthesis (Compilation) Generate Netlist ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

VHDL Firmware Hardware Description
4/24/2018 architecture Behavioral of dpmbufctrl is signal acount : std_logic_vector(31 downto 0); signal dcount : std_logic_vector(31 downto 0); signal bram_addr_i : std_logic_vector(31 downto 0); begin bram_en <='1'; bram_rst <= '0'; --bit order reverse address and data buses to match EDK scheme bram_addr(0 to 31) <= bram_addr_i(31 downto 0); --N.B. EDK DOCM addresses are byte orientated count in 4s for whole words g1 : process(clk, rst) variable state : integer range 0 to 3; variable buf_zone: integer range 0 to 1; if clk'event and clk = '1' then if rst = '1' then buf_zone:=0; acount <= (others => '0'); dcount <= (others => '0'); bram_wen <= (others => '0'); bram_addr_i <= X"00001FFC"; -- bram_dout_i <= (others => '0'); state:=0; elsif state = 0 then --wait for din(0) at address 1FFC to be set to zero --what about pipeline of BRAM - need to wait before polling? bram_addr_i <= X"00001FFC"; dcount <= dcount; if bram_din_i = X" " then state := 1; else state := 0; end if; ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

4/24/2018 View Logic as collection of Processes operating in Parallel Language Constructs for Multiplexers, FlipFlops …etc Restrictive set of RTL for Synthesis Synthesis Tools recognise certain code constructs and generate appropriate logic ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

FPGA Design Synchronous Logic
4/24/2018 Pipelined. Clocked Logic. Combinational and Sequential Logic. Register Transfer Level Logic. ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

VHDL Firmware is Not a Computer Program
4/24/2018 /* C/C++ */ a = 6 /* C/C++ init */ b = 2 /* C/C++ init */ a = b; b = a; /* a = 2 and b = 2 ; sequential */ ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

VHDL Firmware is Not a Computer Program
4/24/2018 But /* C/C++ */ a = 6 /* C/C++ init */ b = 2 /* C/C++ init */ a = b; b = a; /* a = 2 and b = 2 ; sequential */ /* HDL */ a = 6 /* HDL register init */ b = 2 /* HDL register init */ a = b; b = a; /* a = 2 but b = 6 ; concurrent */ ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

4/24/2018 Synthesis (Compilation) Generate Netlist ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Software Languages? 4/24/2018 Can Logic be expressed at a higher level of Abstraction? Familiar to Software Programmer? System C C/C++ Representation of Algorithms Class based Faster simulation Auto translation to HDL Lacks support by Tools Augmented C++ Special Statements to support Concurrency, clocks, pins ..etc Digital Signal Processing Functions ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Firmware Libraries 4/24/2018 Libraries of Firmware aka IP (Intellectual Property), Cores Buy from FPGA Vendor Buy from Third Parties Open Source Libraries VHDL code Black Box NetList Hardwired in Silicon Large User Community ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Debugging Designs Logic Simulation Tools Virtual Logic Analysers
4/24/2018 Logic Simulation Tools Create Computer model of Logic Feed Test Vector signals in and compare output with expected pattern Virtual Logic Analysers Capture signals in real time whilst FPGA is running logic ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

15 Years Evolution SRAM based FPGA devices following Moore’s Law
4/24/2018 SRAM based FPGA devices following Moore’s Law 200 x Logic 40 x Faster Logic Element cost ~ 1$ in 1990 ; $0.002 in 2004 ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Trends State of Art is 65nm on 300 mm wafers
4/24/2018 State of Art is 65nm on 300 mm wafers Top of range 100,000+ Logic Elements 1,000 pins (Ball Grid Arrays) Same cost 1995 : 500 Logic Elements 2000 : 10,000 Logic Elements 2005 : 50,000 Logic Elements Challenges Power. Leakage currents. Signal Integrity Design complexity ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

FPGA Manufactures Market Share
4/24/2018 FPGA Manufactures Market Share $2.1B $2.6B $4.1B $2.6B $2.3B $2.6B $3.1B 100% 31% 33% 34% 32% 31% 32% 32% 80% 60% 39% 32% 28% 24% 20% 18% 17% Market Share (%) 40% 51% 50% 49% 44% 38% 35% 20% 30% 0% Calendar year 1998 1999 2000 2001 2002 2003 2004 Xilinx Altera All Others

Radiation Hardness FPGAs in Standard CMOS Process
4/24/2018 FPGAs in Standard CMOS Process Not Designed for Very Rad Hard environments Not used in Front End Electronics (inside Detectors) Single Event Upsets SRAM Reconfigure Design Logic Triple Redundancy Are used in low level Rad environments (outside Detectors) In satellites On Mars ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

FPGA Research Developments
4/24/2018 High Performance Computing CRAY XD1 : OPTERON + FPGA ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

FPGA Research Developments
4/24/2018 Reconfigurable Computing Virtual Hardware ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

4/24/2018 Summary Q. What does FPGA stand for?

Summary Overview of Field Programmable Gate Arrays
4/24/2018 Summary Overview of Field Programmable Gate Arrays Architecture Programming Design Flows Trends Why they are of interest (in HEP) Thanks for your attention Please come along and visit our electronics lab

4/24/2018 Spare Slides

Choosing an FPGA Vendor Resources Logic Memory I/O pins Packaging
4/24/2018 Vendor Resources Logic Memory I/O pins Packaging Device Families Vendor Tools, IP Cores Special Purpose blocks e.g. CPUs Speed Grade Cost ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

FPGA Packaging FPGA Package is a little PCB Ball Grid Arrays
4/24/2018 FPGA Package is a little PCB Ball Grid Arrays Assembly is a critical Manufacturing Step Signal Integrity Issues ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Special Purpose Blocks
4/24/2018 Digital Signal Processing Functions FIR Filters Digital Radio Advantage over DSP chips Massively Parallel System ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time

Introduction to Field Programmable Gate Arrays FPGAs

Similar presentations

Presentation on theme: "Introduction to Field Programmable Gate Arrays FPGAs"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

Introduction to Field Programmable Gate Arrays FPGAs

Similar presentations

Presentation on theme: "Introduction to Field Programmable Gate Arrays FPGAs"— Presentation transcript:

Similar presentations

About project

Feedback